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Method of fabricating a packaging substrate

a technology of packaging substrate and substrate layer, which is applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical devices, etc., can solve the problems of increasing the overall height of the semiconductor package, increasing affecting the miniaturization of the semiconductor package. achieve the effect of reducing material and fabrication costs, facilitating the thinning of the circuit layer, and improving production efficiency

Inactive Publication Date: 2014-02-27
SILICONWARE PRECISION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention improves the efficiency of packaging substrate production by forming circuit layers on both sides of a carrier, which doubles the number of substrates produced in one process. The carrying portions make the circuit layers thinner and provide strength for subsequent packaging processes. These carrying portions can be removed after packaging to reduce thickness and meet the miniaturization requirement.

Problems solved by technology

However, the core layer 10 increases the thickness of the packaging substrate 1 and consequently increases the overall height of the semiconductor package, thereby hindering miniaturization of the semiconductor package.
Further, the core layer 10 and the conductive through holes 13 increase the material and fabrication cost.
However, the above-described method of fabricating the packaging substrate 1′ has low production efficiency and high fabrication cost since it operates only on a single side of the carrier.
Therefore, the packaging substrate 1′ has to have a certain thickness to ensure sufficient strength during the assembly processes, thereby adversely affecting thinning of the semiconductor package.

Method used

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  • Method of fabricating a packaging substrate
  • Method of fabricating a packaging substrate
  • Method of fabricating a packaging substrate

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first embodiment

[0028]FIGS. 2A to 2G are cross-sectional views showing a method of fabricating a packaging substrate 2 according to the present invention.

[0029]Referring to FIG. 2A, a carrier 2b having two carrying portions 20 bonded together is provided. Each of the carrying portions 20 has a first side 20a with a metal layer 200 and a second side 20b opposite to the first side 20a. The two carrying portions 20 are bonded through the second sides 20b.

[0030]In an embodiment, an adhesive layer 21 is formed in a non-circuit area at edges of the second sides 20b of the carrying portions 20 for bonding the two carrying portions 20. In particular, the adhesive layer 21 is formed at the outside of the circuit area A for bonding the two carrying portions 20. In other embodiments, the adhesive layer 21 can be formed on the entire surfaces of the second sides 20b of the carrying portions 20.

[0031]Referring to FIG. 2A′, each of the carrying portions 20 further has an insulating layer 201, a dielectric layer...

second embodiment

[0052]If the packaging substrate 3 of the second embodiment is used, since the preliminary metal layer 34a is laminated on the metal layer 300, the metal layer 300 can be directly separated from the circuit layer 34. Further, the surface treatment layer 35 on the metal layer 300 is removed.

[0053]Referring to FIG. 4C, a solder mask 28 is formed on the encapsulant 27 and the bottom surface of the circuit layer 24′, and a plurality of openings 280 are formed in the solder mask 28 for exposing a portion of the circuit layer 24′. The chip mounting area 240 can be partially exposed from the openings 280 to serve as a heat dissipating path for the chip 26.

[0054]Referring to FIG. 4D, a plurality of conductive elements 29 such as solder balls are formed on the exposed portion of the circuit layer 24, and a singulation process is performed along a cutting line S of FIG. 4C to obtain a plurality of semiconductor packages 2a, 2a′.

[0055]According to the present invention, since the carrying por...

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Abstract

A method of fabricating a packaging substrate is provided, including: providing a carrier having two carrying portions, each of the carrying portions having a first side and a second side opposite to the first side and the carrying portions are bonded through the second sides thereof; forming a circuit layer on the first side of each of the carrying portions; and separating the two carrying portions from each other to form two packaging substrates. The carrying portions facilitate the thinning of the circuit layers and provide sufficient strength for the packaging substrates to undergo subsequent packaging processes. The carrying portions can be removed after the packaging processes to reduce the thickness of packages and thereby meet the miniaturization requirement.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to packaging substrates, and, more particularly, to a method of fabricating a packaging substrate having a carrying portion.[0003]2. Description of Related Art[0004]Along with the rapid development of electronic industries, electronic products are developed towards miniaturization, multi-function and high performance. Accordingly, packaging substrates used for carrying chips are required to have a small thickness to meet the miniaturization requirement of semiconductor packages.[0005]FIG. 1A is a cross-sectional view illustrating the fabrication of a conventional semiconductor package using a packaging substrate 1 having a core layer 10. The core layer 10 increases the strength of the overall structure to facilitate subsequent chip mounting and packaging processes. Referring to FIG. 1A, the packaging substrate 1 further has: the dielectric layer 11 formed on two opposite sides of the core l...

Claims

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Application Information

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IPC IPC(8): H01L21/78
CPCH01L21/78H01L21/4846H01L24/97H01L2224/32225H01L2224/48091H01L2224/48227H01L2224/48228H01L2224/73265H01L2924/15184H01L2924/15311H01L2924/00014H01L23/3128H01L21/561H01L21/568H01L21/6835H01L24/48H01L2221/68345H01L2224/97H01L2924/181H01L2924/00H01L2224/45099H01L2924/00012H01L21/4857H01L23/49838H01L2221/68359
Inventor PAI, YU-CHENGLIN, CHUN-HSIENHSIAO, WEI-CHUNGSUN, MING-CHENHUNG, LIANG-YI
Owner SILICONWARE PRECISION IND CO LTD