Finfet formed over dielectric

Abstract

A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels. A thermal oxidation is performed to diffuse elements from the semiconductor layer into an upper portion of the one or more mandrels and concurrently oxidize a lower portion of the one or more mandrels to form the one or more mandrels on the dielectric material.

Description

BACKGROUND[0001]1. Technical Field[0002]The present invention relates to semiconductor fabrication, and more particularly to the formation of silicon germanium fins and bottom dielectric isolation together.[0003]2. Description of the Related Art[0004]Current techniques for forming pFET (p-type field effect transistor) silicon germanium fins include forming a silicon well in the pFET region, growing silicon germanium, and then forming fins from the silicon germanium through advanced patterning techniques. However, one challenge of this approach is the high germanium concentration in the silicon germanium epitaxial growth. When germanium concentration is too high, it can result in defects and may also lose epitaxial growth selectivity. Another challenge is that the current techniques require sufficient spacing between silicon fins (e.g., in the n-type field effect transistor region) and silicon germanium fins (e.g., in the pFET region) so that the fins formed close to the boundary bet...

AI Technical Summary

Benefits of technology

This approach effectively forms silicon germanium fins with bottom dielectric isolation, improving epitaxial growth selectivity and reducing unnecessary area, enhancing performance by allowing closer fin placement without defects.

Problems solved by technology

However, one challenge of this approach is the high germanium concentration in the silicon germanium epitaxial growth.

When germanium concentration is too high, it can result in defects and may also lose epitaxial growth selectivity.

Another challenge is that the current techniques require sufficient spacing between silicon fins (e.g., in the n-type field effect transistor region) and silicon germanium fins (e.g., in the pFET region) so that the fins formed close to the boundary between them can be cut off in later processing.

This requirement adds to cell density and causes an increase in area without any performance benefit, such as, e.g., reduced current drive per footprint.

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