Well resistors and polysilicon resistors

Abstract

An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.

Description

FIELD OF THE INVENTION[0001]This invention relates to the field of integrated circuits. More particularly, this invention relates to resistors in integrated circuits.BACKGROUND OF THE INVENTION[0002]An integrated circuit containing field oxide made by a shallow trench isolation (STI) process includes an oxide planarization step using a chemical mechanical polish (CMP) process. The CMP process overpolishes large areas of low active area density, such as resistor areas, producing thin field oxide in these areas with unpredictable thickness profiles. Well resistors made under overpolished field oxide have low, erratic resistance due to more implanted dopants passing through the thin field oxide. Resistors of polycrystalline silicon, referred to as polysilicon, on overpolished field oxide, in which the polysilicon has been planarized with another CMP process, tend to have high, erratic, thicknesses leading to low, variable resistance and undesired variation in temperature dependence of ...

AI Technical Summary

Benefits of technology

This approach ensures consistent and desired resistance values for both well resistors and polysilicon resistors by maintaining a controlled thickness of the field oxide, reducing variability and temperature dependence, thus improving the reliability of integrated circuits.

Problems solved by technology

The CMP process overpolishes large areas of low active area density, such as resistor areas, producing thin field oxide in these areas with unpredictable thickness profiles.

Well resistors made under overpolished field oxide have low, erratic resistance due to more implanted dopants passing through the thin field oxide.

Resistors of polycrystalline silicon, referred to as polysilicon, on overpolished field oxide, in which the polysilicon has been planarized with another CMP process, tend to have high, erratic, thicknesses leading to low, variable resistance and undesired variation in temperature dependence of the resistance.

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