System for reducing power consumption of integrated circuit

Abstract

A method for reducing dynamic power consumption of an integrated circuit design having flip-flops with an EDA tool that initiates clock gating by gating a clock signal received by the flip-flops. A first set of positive-edge triggered flip-flops and a second set of negative-edge triggered flip-flops, and a first set of OR-type clock gating cells and a second set of AND-type clock gating cells are selected from a technology library. The OR-type clock gating cells are connected to clock input terminals of the first set of positive-edge triggered flip-flops and the AND-type clock gating cells to clock terminals of the second set of negative-edge triggered flip-flops.

Description

BACKGROUND OF THE INVENTION[0001]The present invention relates generally to electronic design automation (EDA) tools, and, more particularly, to an EDA tool capable of modifying an integrated circuit design for reduced dynamic power consumption.[0002]Integrated circuits (ICs), such as systems-on-chip (SoCs) include combinational and sequential logic elements including flip-flops and latches that operate based on toggling of a clock signal received by the SoC. The flip-flops and latches consume a significant amount of power. The outputs of the flip-flops and latches change at every edge of the clock signal, which adds to the power consumption because the power consumed is directly proportional to operational voltage and operational frequency of the clock signal. The magnitude of the power consumed can be calculated using the equation (1):Power consumed=α*C*V2*F  (1)where,α=switching factor of the clock signal,C=load capacitance that is charged or discharged during each cycle of the c...

AI Technical Summary

Problems solved by technology

The flip-flops and latches consume a significant amount of power.

The outputs of the flip-flops and latches change at every edge of the clock signal, which adds to the power consumption because the power consumed is directly proportional to operational voltage and operational frequency of the clock signal.

Reducing the operational frequency of the clock signal affects circuit performance, while reducing the operational voltage increases propagation delays of the logic circuits.

However, when the logic state of the enable control signal toggles between two pulses of the clock signal, the gated clock signal is either terminated prematurely or generates multiple clock pulses with indeterminate time periods.

Hence, any change at a data input terminal of the master latch of each positive-edge triggered flip-flop is reflected at an output terminal of the master latch, thereby increasing internal dynamic power consumption of the positive-edge triggered flip-flops during idle state.

However, a SoC includes thousands of positive-edge triggered flip-flops and each requires a dedicated multiplexer connected at its data input terminal, which drastically increases chip area.

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