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Method of forming a semiconductor structure including a plurality of fins and an alignment/overlay mark

a technology of alignment/overlay mark and semiconductor structure, which is applied in the manufacturing of semiconductor/solid-state devices, electric devices, solid-state devices, etc., can solve the problems of compromising the functionality of overlay/alignment mark in later manufacturing processes, limiting the possibility of forming small features by conventional techniques of photolithography and etching, and affecting the quality of the finished produ

Inactive Publication Date: 2016-07-14
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach helps maintain the integrity of overlay / alignment marks by ensuring larger dimensions and reducing the risk of collapse, thereby improving the alignment and functionality in later manufacturing stages.

Problems solved by technology

However, the possibility of forming small features by means of conventional techniques of photolithography and etching may be limited by the resolution of the photolithography process.
However, using overlay / alignment marks in combination with sidewall image transfer techniques as described above may have some issues associated therewith, in particular when a double sidewall image transfer technique is employed.
Since patterning conditions of the sidewall image transfer processes are typically adapted for fin patterns that are employed for providing FinFET transistors and / or Tri-Gate transistors, the fins that are formed from the overlay / alignment mark features may be vulnerable to collapsing, which can create defects in the semiconductor structure and compromise the functionality of the overlay / alignment marks in later manufacturing processes.
However, in this case, the alignment / overlay marks typically include relatively deep trenches in the substrate, into which the layer stack that includes mandrel layers and etch stop layers for use in the sidewall image transfer techniques is filled, and the sidewall image transfer stack may have to be pulled out from the overlay / alignment marks by means of additional steps of the manufacturing process, which may increase the complexity of the manufacturing process.
However, in this case, the first set of overlay / alignment marks may still be a defect source in later stages of the manufacturing process due to collapsing fins, and later stages of the manufacturing process may be adversely affected by alignment errors in the formation of the second set of overlay / alignment marks.
Other techniques may include a pitch reduction in overlay / alignment marks which, however, may be insufficient for preventing a collapse of fins.

Method used

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  • Method of forming a semiconductor structure including a plurality of fins and an alignment/overlay mark
  • Method of forming a semiconductor structure including a plurality of fins and an alignment/overlay mark
  • Method of forming a semiconductor structure including a plurality of fins and an alignment/overlay mark

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Embodiment Construction

[0024]Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

[0025]The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details ...

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Abstract

A method includes providing a semiconductor structure including a substrate that includes a material to be patterned. First and second mandrels are formed over the substrate using a common photolithography process that defines a position of the first mandrel relative to the substrate and a position of the second mandrel relative to the substrate. A first sidewall spacer is formed adjacent the first mandrel and a second sidewall spacer is formed adjacent the second mandrel. After the formation of the first and the second sidewall spacers, the first mandrel is removed. The second mandrel remains in the semiconductor structure. A first mask element is provided on the basis of the first sidewall spacer. A second mask element is provided on the basis of the second mandrel and the second sidewall spacer. The material to be patterned is patterned on the basis of the first and the second mask elements.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]Generally, the present disclosure relates to methods for the manufacturing of integrated circuits, and, in particular, to methods for the manufacturing of integrated circuits wherein sidewall image transfer techniques are employed.[0003]2. Description of the Related Art[0004]Integrated circuits include a large number of circuit elements which include, in particular, field effect transistors. In a field effect transistor, a gate electrode is provided that may be separated from a channel region by a gate insulation layer providing an electrical insulation between the gate electrode and the channel region. Adjacent the channel region, a source region and a drain region are formed, which are doped differently than the channel region. In addition to planar transistors, transistors that can be used in integrated circuits include transistors wherein the channel region is formed in one or more elongated semiconductor regions, w...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/8234H01L21/027H01L21/308H01L21/02H01L21/311H01L21/306
CPCH01L21/823412H01L21/823431H01L21/31116H01L21/31144H01L21/30604H01L21/0276H01L21/02164H01L21/0217H01L21/02532H01L21/02592H01L21/3081H01L21/845H01L27/1211H01L21/0337H01L21/32139
Inventor SUNG, MIN GYUPARK, CHANROKIM, HOONXIE, RUILONG
Owner GLOBALFOUNDRIES INC