Memory device and operation method

Active Publication Date: 2016-11-10
MACRONIX INT CO LTD
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Benefits of technology

[0005]The invention provides a memory device and an operation method thereof According to the memory device and the operation method thereof, whether to write an error correction code corresponding to an original

Problems solved by technology

Thus, in the conventional memory devices, each data in the phase-change memories has a corresponding error correction code, which results in a large amo

Method used

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  • Memory device and operation method
  • Memory device and operation method
  • Memory device and operation method

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[0017]Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0018]FIG. 1 is a schematic view illustrating a memory device according to an embodiment of the invention. Referring to FIG. 1, a memory device 100 includes memory arrays 111 and 112, buffer circuits 121 and 122, an encoding circuit 130, and an error correction circuit 140. In addition, the memory array 111 may store original data, and the memory array 112 may store error correction codes (ECC) corresponding to the original data. It should be noted that the memory device 100 determines whether to write the error correction codes corresponding to the original data into the memory array 112 according to a verification result of a programming operation of the original data. Accordingly, the memory devic...

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Abstract

A memory device and an operation method thereof are provided, and the operation method of the memory device includes following steps. A programming operation is performed to write an original data into a first memory array in the memory device. The original data in the first memory array is verified, and whether to generate a write signal is determined according to a verification result. An error correction code is generated according to the original data, and the error correction code and a write address are stored temporarily in a buffer circuit of the memory device. When the write signal is generated, the error correction code and the write address in the buffer circuit are written into a second memory array in the memory device.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The invention relates to a memory device and an operation method thereof, and particularly relates to a memory device having an error correction code and an operation method thereof.[0003]2. Description of Related Art[0004]Recently, phase-change memories have become the prospective non-volatile memory technology due to the advantages of low voltage, low power consumption, and high integration in the manufacturing processes, etc. Generally speaking, to ensure the accuracy of data in the phase-change memories, the conventional memory devices commonly store a corresponding error correction code (ECC) for each data in the phase-change memories. Thus, in the conventional memory devices, each data in the phase-change memories has a corresponding error correction code, which results in a large amount of memory space being required to store the error correction codes. The development of miniaturization of the memory devices is ...

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Application Information

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IPC IPC(8): G06F11/10G06F3/06
CPCG06F11/1076G06F3/0683G06F3/064G06F3/0619G06F11/1048
Inventor HO, HSIN-YILUNG, HSIANG-LANCHIEN, WEI-CHIHCHEN, TU-SHUNCHEN, CHIA-JUNG
Owner MACRONIX INT CO LTD
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