Event router and routing method for symmetric multiprocessor virtual machine using queue
a multi-processor virtual machine and event routing technology, applied in the direction of interprogram communication, multi-programming arrangements, program control, etc., can solve the problems of event processing delay, delay greatly influences input/output performance, and more problems, so as to reduce the time consumed by event processing delay
Inactive Publication Date: 2016-12-15
ELECTRONICS & TELECOMM RES INST
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- Description
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Benefits of technology
The present invention aims to reduce delays and improve the efficiency of event processing by utilizing information provided by a hypervisor. The technical effect of the invention is to speed up the event processing process.
Problems solved by technology
Since an existing SMP is configured such that multiple CPUs are operated in a single system, there are more problems that must be taken into consideration than in the case of a Uni-processor (UP).
One of the problems is determining to which of the CPUs belonging to the SMP an event is to be delivered.
When an event is delivered to a vCPU in an operating state, it may be immediately processed, whereas when an event is delivered to a vCPU in a stopped state, an event processing delay occurs, due to which the event cannot be processed until the vCPU enters an operating state.
Such an event processing delay greatly influences Input / Output (I / O) performance.
However, this scheme is very inefficient from the standpoint of the above-described problem.
However, Korean Patent Application Publication No. 10-2012-0063436 merely discloses technology for distributing loads to CPUs that are always in an operating state, and cannot be applied to a vCPU that repeatedly enters a stopped state and an operating state.
Method used
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[0043]The present invention will be described in detail below with reference to the accompanying drawings. Repeated descriptions and descriptions of known functions and configurations which have been deemed to make the gist of the present invention unnecessarily obscure will be omitted below. The embodiments of the present invention are intended to fully describe the present invention to a person having ordinary knowledge in the art to which the present invention pertains. Accordingly, the shapes, sizes, etc. of components in the drawings may be exaggerated to make the description clearer.
[0044]First, the terms used in the present specification will be defined as follows.
[0045]The term “event” denotes not all events, but only an event that causes no problem even if it is delivered to any one of the virtual CPUs (vCPUs) in SMP virtual machine that receives the event. For example, such an event may refer to all signals causing interrupts in the vCPUs, such as an Interrupt Request (IRQ...
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Disclosed herein are an event router and an event routing method for a virtual machine using a queue. The event router includes an event delivery decision unit for deciding on a method of delivering an event that is provided to a hypervisor, based on state information of virtual Central Processing Units (vCPUs) used by a Symmetric Multiprocessor (SMP) virtual machine, and an event delivery unit for delivering the event to a relevant virtual CPU based on both the event delivery method and the state information.
Description
CROSS REFERENCE TO RELATED APPLICATION[0001]This application claims the benefit of Korean Patent Application No. 10-2015-0081125, filed Jun. 9, 2015, which is hereby incorporated by reference in its entirety into this application.BACKGROUND OF THE INVENTION[0002]1. Technical Field[0003]The present invention generally relates to technology for routing the event of a Symmetric Multiprocessor (SMP) virtual machine and, more particularly, to event routing technology that may be applied to a hypervisor for managing and running virtual machines so as to minimize the delay of event processing.[0004]2. Description of the Related Art[0005]A Symmetric Multiprocessor (SMP) (or symmetric multiprocessing system) is a system in which multiple Central Processing Units (CPUs) having the same performance are used in a single shared memory space. An SMP is a system designed to overcome the limitations in the performance of a Uni-processor (UP) system, which uses a single CPU.[0006]Such an SMP has bee...
Claims
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IPC IPC(8): G06F9/455G06F9/54
CPCG06F9/542G06F9/45558G06F2009/45595
Inventor SHIN, JUNG-SUB
Owner ELECTRONICS & TELECOMM RES INST