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Apparatuses and methods for charging a global access line prior to accessing a memory

a global access and memory technology, applied in the direction of information storage, static storage, instruments, etc., can solve the problems of significant increase in the read latency of the memory, longer wordline wait time,

Active Publication Date: 2017-03-09
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent text describes an apparatus and method for improving the performance of non-volatile memories, such as flash memories, by reducing latency and improving read latency. The invention involves charging global access lines and drivers to a read access voltage before accessing the memory, and providing an address buffer to enable efficient access to the memory. The invention also includes a data cache for storing and retrieving data from the memory. The technical effects of the invention include reducing latency and improving read latency, as well as improving the performance of non-volatile memories in general.

Problems solved by technology

As a result, wordline wait time becomes longer, and the read latency of the memories may increase significantly.

Method used

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  • Apparatuses and methods for charging a global access line prior to accessing a memory
  • Apparatuses and methods for charging a global access line prior to accessing a memory
  • Apparatuses and methods for charging a global access line prior to accessing a memory

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Embodiment Construction

[0009]Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one skilled in the art that embodiments of the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the invention.

[0010]FIG. 1 illustrates an apparatus including a memory 100 according to an embodiment of the invention. As used herein, apparatus may refer to, for example, an integrated circuit, a memory device, a memory system, an electronic device or system, a smart phone, a tablet, a computer, a server, etc.

[0011]The memory 100 also includes, for example, a memory ar...

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Abstract

Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a memory. A plurality of global access lines may be associated with the memory array. The global access line may be charged to a ready-access voltage before any access command has been received by the memory. The global access line may be maintained at the ready-access voltage during memory access operations until the receipt of a post-access command. The post-access command may reset the global access line to an inactive voltage.

Description

BACKGROUND OF THE INVENTION[0001]Memories may be provided in a variety of apparatuses, such as computers or other devices, including but not limited to portable memory devices, solid state drives, music players, cameras, phones, wireless devices, displays, chip sets, set top boxes, gaming systems, vehicles and appliances. There are many different types of memory including volatile memory (e.g., dynamic random access memory (DRAM)) and non-volatile memory (e.g., flash memory). Flash memory architectures may include NAND or NOR architecture.[0002]As the physical size of non-volatile memories (e.g., NAND flash memories) decreases, capacitance related to the global wordlines can significantly increase due to an increased number of local wordlines and drivers. As a result, wordline wait time becomes longer, and the read latency of the memories may increase significantly.BRIEF DESCRIPTION OF THE DRAWINGS[0003]FIG. 1 is a block diagram of an apparatus including a memory according to an emb...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G11C16/26G11C16/08
CPCG11C16/08G11C16/26G11C16/30G11C16/32G11C16/0483
Inventor TANZAWA, TORU
Owner MICRON TECH INC