Precise control of vertical transistor gate length

Abstract

Transistor and methods of forming the same include forming a channel fin on a bottom source / drain region. A dielectric fill is formed around the channel fin with a gap in an area directly above the channel fin that has a width greater than a width of the channel fin. Spacers are formed in the gap. The dielectric fill is etched away. A gate stack is formed on sidewalls of the channel fin directly underneath the spacers.

Description

BACKGROUNDTechnical Field[0001]The present invention generally relates to semiconductor devices and, more particularly, to the use of an L-shaped spacer for decreasing variations in vertical transistor gate length.Description of the Related Art[0002]Vertical transistors employ channel regions that are oriented generally perpendicular to the plane of an underlying substrate—as opposed to conventional transistors which generally have channel regions that are a part of, or are otherwise parallel to, the underlying substrate. This orientation has significant potential for device scaling, more transistors can fit within a given chip surface area.[0003]However, one challenge in forming a vertical transistor is in controlling the device's gate length. The gate length determines various properties of the final device, and conventional fabrication processes result in significant variation in gate length from one device to the next.SUMMARY[0004]A method for forming a transistor includes formi...

AI Technical Summary

Benefits of technology

The patent describes methods for making transistors with improved performance. The methods involve forming a channel fin on a bottom source / drain region and etching away a dielectric fill to create a gap above the channel fin. Spacers are then formed in the gap and a gate stack is formed on sidewalls of the channel fin. This allows for better control and performance of the transistor. The methods can be implemented in a vertical transistor design or in a design with another structure, like a covering layer. The technical effects of this patent are to improve the performance and control of transistors in a specific design.

Problems solved by technology

However, one challenge in forming a vertical transistor is in controlling the device's gate length.

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