6 results about "Transistor design" patented technology

Various embodiments disclosed presents pixel driver circuits that utilize integrated diode structures to enhance sub-threshold swing and modulate threshold voltage. Conventional transistor-only designs often encounter challenges in achieving precise control and efficiency, limited by their sub-threshold swing and voltage modulation capabilities. Various embodiments incorporate advanced MOSFETs in series with diodes without an additional mask and process knob, enabling advanced control over the LED current without a larger area penalty and less process variation with device sub-threshold engineering. Such transistor-diode configuration improves brightness, gray-scale accuracy, and overall display performance, leading to improved power efficiency, advanced display uniformity, and improved reliability for LED devices.

A light-emitting display device according to one or more embodiments of the present disclosure can comprise a display panel with multiple subpixels connected by data lines, gate lines, and gate drive voltage lines, a data drive circuit designed to supply data signals to the data lines, and a gate drive circuit designed to supply sampling signals to the gate lines, wherein each of the multiple subpixels comprises a light-emitting device, a drive transistor designed to connect between the gate drive voltage line and the light-emitting device and to control a current flowing through the light-emitting device, a first switching transistor designed to connect between a first node of the drive transistor and the data line, and a second switching transistor designed tobetween a second node of the drive transistor, which is connected to the light-emitting device, and the data line, may include a first capacitor connected between the first node and the second node, and a second capacitor connected between a third node of the drive transistor, which is connected to the drive voltage line, and the second node.

The invention relates to insulated gate bipolar transistor designs and methods. An insulated gate bipolar transistor includes a plurality of semiconductor layers, a trench material, an electrically insulating layer, and an emitter conductive layer. The semiconductor layer has (i) a semiconductor surface and (ii) a plurality of gate trenches and a plurality of emitter trenches formed through the semiconductor surface separated by a plurality of mesas. The trench material is disposed in the emitter trenches. The electrically insulating layer is formed over the semiconductor layers. The electrically insulating layer defines a plurality of openings aligned with the mesas and extending across the emitter trenches. The electrically insulating layer does not extend into the emitter trenches. The emitter conductive layer is formed over the electrically insulating layer. The emitter conductive layer directly contacts (i) each mesa and (ii) the trench material in each emitter trench through the openings. The emitter conductivity also extends across the emitter trenches.

Method for operating a semiconductor device, comprising: - Accessing the semiconductor device, which contains multi-stage storage transistors arranged in rows and columns, wherein the multi-stage storage transistors include silicon-oxide-nitride-oxide-silicon (SONOS)-based charge-trapping transistors designed to store one of N x analog values ​​corresponding to the N levels of a threshold voltage, VT, and a drain current, ID, where N is a natural number greater than 2; - Selecting at least one of the multi-stage storage transistors for a write operation to a setpoint, wherein the setpoint is one of the N x analog values ​​and corresponds to a setpoint ID range extending from a setpoint ID lower bound, LL, to a setpoint ID upper bound, UL;- Performing a partial programming operation on the at least one of the multi-stage storage transistors for ID level reduction, wherein the partial programming operation comprises at least one soft programming operation and one padding programming operation, wherein the partial programming operation is designed to reduce the ID level and increase a VT level for the at least one of the multi-stage storage transistors, and wherein multi-stage storage transistors not selected for the partial programming operation are disabled, wherein an initial check read is performed after the partial programming operation to determine how a reduced ID level compares to a target ID mean;- Performing a partial erase operation on at least one of the multi-stage storage transistors to raise the ID level, wherein the partial erase operation comprises at least one of a soft erase operation, a selective soft erase operation, and an annealing erase operation, wherein the partial erase operation is designed to raise the ID level and decrease the VT level for at least one of the multi-stage storage transistors, and wherein multi-stage storage transistors not selected for the selective soft erase operation are disabled, wherein a second check read is performed after the partial erase operation to determine how a raised ID level compares to the target ID mean; and - Determining that the write operation to the target value is complete when the ID level of the at least one of the multi-stage storage transistors falls within the target ID range.

The invention discloses an array substrate, a preparation method thereof and a display panel. The array substrate comprises a substrate, a first transistor and a second transistor. The first transistor located in the middle area comprises a first active layer, and the material of the first active layer comprises oxide. The second transistor in the side region comprises a second active layer, and the material of the second active layer comprises silicon, that is, the middle region is an oxide transistor, and the side region is a silicon transistor. Transistors of different materials are designed in different areas, when scanning crystallization is carried out on the array substrate, selective scanning silicon transistor areas, namely selective scanning side edge areas and middle areas, can rapidly pass through in the scanning process, the production takt is effectively improved, the effect of reducing the process operation cost and the production cost is achieved, and the production efficiency is improved. Therefore, the processing property of a display product is improved.

Image element, encompassing - a first and a second supply connection (11, 12), - a light-emitting semiconductor device (13), - a driver circuit (14) comprising a driver transistor (16), a storage capacitor (17) and a switching transistor (30), and - a flip-flop circuit (31) which is monostable and comprises an output transistor (33), a control resistor (36) and a control capacitor (34), wherein the light-emitting semiconductor device (13) and the driver transistor (16) are arranged in series with each other and between the first supply terminal (11) and the second supply terminal (12), wherein a first electrode of the storage capacitor (17) is coupled to a control terminal of the driver transistor (16), wherein the switching transistor (30) is designed to switch on and off a current flow (IL) through the light-emitting semiconductor device (13), wherein a first electrode of the control capacitor (34) is connected to a control terminal of the output transistor (33), wherein a second electrode of the control capacitor (34) is coupled to the first supply terminal (11), wherein a first terminal of the output transistor (33) is connected to a control terminal of the switching transistor (30), wherein the control capacitor (34) couples the control terminal of the output transistor (33) to a second terminal of the output transistor (33), and wherein the control resistor (36) is coupled to the first electrode of the control capacitor (34) and to a second electrode of the control capacitor (34).