13 results about "Transistor design" patented technology

Various embodiments disclosed presents pixel driver circuits that utilize integrated diode structures to enhance sub-threshold swing and modulate threshold voltage. Conventional transistor-only designs often encounter challenges in achieving precise control and efficiency, limited by their sub-threshold swing and voltage modulation capabilities. Various embodiments incorporate advanced MOSFETs in series with diodes without an additional mask and process knob, enabling advanced control over the LED current without a larger area penalty and less process variation with device sub-threshold engineering. Such transistor-diode configuration improves brightness, gray-scale accuracy, and overall display performance, leading to improved power efficiency, advanced display uniformity, and improved reliability for LED devices.

The invention relates to the technical field of metal oxide semiconductor field effect transistor design, and discloses a leakage current testing device and a preparation method thereof, and a method for determining the length of a gate end cap, and the leakage current testing device comprises a semiconductor substrate layer which is provided with an active region; the gate structure is located on the active region, the length of the gate end cover is a first preset length, and the length of the gate end cover is the length, exceeding the active region, of the gate structure in the preset direction; the metal through hole is formed in the active region; the metal leads are located on the two sides of the active area in the preset direction, one end of each metal lead is connected with the corresponding metal through hole, the other end of each metal lead is connected with a metal bonding pad of the power supply, and the active area is connected with the power supply to determine the leakage current corresponding to the first preset length. According to the invention, the accuracy of the leakage current corresponding to the length of the tested gate end cover can be improved.

A light-emitting display device according to one or more embodiments of the present disclosure can comprise a display panel with multiple subpixels connected by data lines, gate lines, and gate drive voltage lines, a data drive circuit designed to supply data signals to the data lines, and a gate drive circuit designed to supply sampling signals to the gate lines, wherein each of the multiple subpixels comprises a light-emitting device, a drive transistor designed to connect between the gate drive voltage line and the light-emitting device and to control a current flowing through the light-emitting device, a first switching transistor designed to connect between a first node of the drive transistor and the data line, and a second switching transistor designed tobetween a second node of the drive transistor, which is connected to the light-emitting device, and the data line, may include a first capacitor connected between the first node and the second node, and a second capacitor connected between a third node of the drive transistor, which is connected to the drive voltage line, and the second node.

A device is disclosed herein. The device comprises a first power supply rail, a second power supply rail, an electrical protection component conductively coupled between the first and second power supply rails, wherein the electrical protection component is designed to monitor a voltage property of the power supply rail in order to detect an electrical event, and a thermal protection component conductively coupled between the power supply rails and to the electrical protection component, wherein the thermal protection component comprises a temperature-sensitive transistor designed to change an electrical property of the electrical protection component in response to a temperature change of the device.

The invention discloses an ion sensitive field effect transistor and a manufacturing method thereof, the ion sensitive field effect transistor can be used in the field of semiconductors, and a grid electrode of the ion sensitive field effect transistor is of a three-layer structure; the grid electrode comprises a first material layer, a second material layer and a columnar array structure; the first material layer is located on the side, close to the substrate, of the gate, the second material layer is located on the side, away from the substrate, of the gate, and the columnar array structure is located between the first material layer and the second material layer. Therefore, a grid electrode with a three-layer structure is designed for the ion sensitive field effect transistor, compared with a traditional plane structure, the columnar array structure has a larger specific surface area, more targeted molecule modification sites can be provided, the interaction between targeted molecules and a to-be-detected substance is enhanced, the interface potential change is more remarkable, and the detection sensitivity is improved. And the detection sensitivity of the ion sensitive field effect transistor is effectively improved.

The utility model relates to a power tube temperature detection device which is used for detecting the temperature of a power tube in a power level chip. The power tube temperature detection device comprises a first bonding pad arranged on a driving controller chip; the second bonding pad is arranged at the source electrode of the power tube on the power tube chip; the two ends of the bonding wire are welded to the first bonding pad and the second bonding pad respectively; and the temperature detection circuit is arranged on the driving controller chip and is used for detecting the temperature of the first bonding pad and outputting a temperature detection signal to the driving controller chip. The temperature detection device realizes temperature transmission through wire bonding, on one hand, the temperature detection device can be compatible with the existing power tube design, a power tube chip does not need to be redesigned by spending a large amount of cost, on the other hand, compared with a temperature gradient detection scheme in the existing design, the temperature of the power tube can be detected more accurately and rapidly, and the detection efficiency is improved. And higher reliability is provided.

The invention relates to insulated gate bipolar transistor designs and methods. An insulated gate bipolar transistor includes a plurality of semiconductor layers, a trench material, an electrically insulating layer, and an emitter conductive layer. The semiconductor layer has (i) a semiconductor surface and (ii) a plurality of gate trenches and a plurality of emitter trenches formed through the semiconductor surface separated by a plurality of mesas. The trench material is disposed in the emitter trenches. The electrically insulating layer is formed over the semiconductor layers. The electrically insulating layer defines a plurality of openings aligned with the mesas and extending across the emitter trenches. The electrically insulating layer does not extend into the emitter trenches. The emitter conductive layer is formed over the electrically insulating layer. The emitter conductive layer directly contacts (i) each mesa and (ii) the trench material in each emitter trench through the openings. The emitter conductivity also extends across the emitter trenches.

Memory cell (102), comprising: a write bit line; a write transistor (M1, M1') coupled between the write bit line and a first node (ND1); and a read transistor (M2, M2') which is coupled to the write transistor (M1, M1') via the first node (ND1); wherein the read transistor (M2, M2') has a ferroelectric layer (202, 520) and the write transistor (M1, M1') is designed to set a stored data value of the memory cell (102) by means of a write bit line signal which sets a polarization state of the read transistor, wherein the polarization state corresponds to the stored data value; where the write transistor (M1, M1') has: a first drain terminal that is coupled to the write bit line; a first source terminal coupled to the first node (ND1) and the read transistor (M2, M2'); and a first gate connection that is coupled to a write word line; where the read transistor (M2, M2') has: a second drain connection coupled to a second node; a second source port that is coupled to a third node; and a second gate terminal on the ferroelectric layer (202, 520) which is coupled to the first source terminal via the first node (ND1); wherein the memory cell (102) further comprises: a first transistor (M3, M3') coupled to the read transistor (M2, M2'), wherein the first transistor has: a third drain port that is coupled to the second source port via the third node; a third source port coupled with a read bit line; and a third gate connector; wherein the second drain terminal is coupled to a reference voltage supply via the second node; and the third gate connection is coupled with a read word line; and wherein the memory cell (102) further comprises: a second transistor (M4, M4') coupled via the first node (ND1) to the read transistor (M2, M2') and the write transistor (M1, M1'), the second transistor comprising: a fourth drain connection that is coupled to the read word line; a fourth source port coupled to a fourth node (ND2); and a fourth gate connection, which is coupled via the first node (ND1) to the first source connection and the second gate connection.

Method for operating a semiconductor device, comprising: - Accessing the semiconductor device, which contains multi-stage storage transistors arranged in rows and columns, wherein the multi-stage storage transistors include silicon-oxide-nitride-oxide-silicon (SONOS)-based charge-trapping transistors designed to store one of N x analog values ​​corresponding to the N levels of a threshold voltage, VT, and a drain current, ID, where N is a natural number greater than 2; - Selecting at least one of the multi-stage storage transistors for a write operation to a setpoint, wherein the setpoint is one of the N x analog values ​​and corresponds to a setpoint ID range extending from a setpoint ID lower bound, LL, to a setpoint ID upper bound, UL;- Performing a partial programming operation on the at least one of the multi-stage storage transistors for ID level reduction, wherein the partial programming operation comprises at least one soft programming operation and one padding programming operation, wherein the partial programming operation is designed to reduce the ID level and increase a VT level for the at least one of the multi-stage storage transistors, and wherein multi-stage storage transistors not selected for the partial programming operation are disabled, wherein an initial check read is performed after the partial programming operation to determine how a reduced ID level compares to a target ID mean;- Performing a partial erase operation on at least one of the multi-stage storage transistors to raise the ID level, wherein the partial erase operation comprises at least one of a soft erase operation, a selective soft erase operation, and an annealing erase operation, wherein the partial erase operation is designed to raise the ID level and decrease the VT level for at least one of the multi-stage storage transistors, and wherein multi-stage storage transistors not selected for the selective soft erase operation are disabled, wherein a second check read is performed after the partial erase operation to determine how a raised ID level compares to the target ID mean; and - Determining that the write operation to the target value is complete when the ID level of the at least one of the multi-stage storage transistors falls within the target ID range.

The application relates to a low-power-consumption small-area high-PSR full-MOS voltage reference circuit and equipment, which adopts a depletion-mode MOS transistor and an enhancement-mode transistor to design a reference current generation circuit and a core reference circuit on a circuit process, so that a tiny reference current can be generated under a smaller circuit area, a full-MOS transistor structure design is adopted on a core circuit structure, the area cost of the circuit is greatly saved, a power supply voltage preprocessing circuit is designed to provide power supply voltage preprocessing, the PSR of the full-MOS voltage reference circuit is effectively improved, the full-MOS voltage reference circuit has the characteristics of low power consumption, small area and high PSR, and the purpose of designing a low-power-consumption small-area high-PSR voltage reference circuit is achieved.

The invention discloses an array substrate, a preparation method thereof and a display panel. The array substrate comprises a substrate, a first transistor and a second transistor. The first transistor located in the middle area comprises a first active layer, and the material of the first active layer comprises oxide. The second transistor in the side region comprises a second active layer, and the material of the second active layer comprises silicon, that is, the middle region is an oxide transistor, and the side region is a silicon transistor. Transistors of different materials are designed in different areas, when scanning crystallization is carried out on the array substrate, selective scanning silicon transistor areas, namely selective scanning side edge areas and middle areas, can rapidly pass through in the scanning process, the production takt is effectively improved, the effect of reducing the process operation cost and the production cost is achieved, and the production efficiency is improved. Therefore, the processing property of a display product is improved.

Image element, encompassing - a first and a second supply connection (11, 12), - a light-emitting semiconductor device (13), - a driver circuit (14) comprising a driver transistor (16), a storage capacitor (17) and a switching transistor (30), and - a flip-flop circuit (31) which is monostable and comprises an output transistor (33), a control resistor (36) and a control capacitor (34), wherein the light-emitting semiconductor device (13) and the driver transistor (16) are arranged in series with each other and between the first supply terminal (11) and the second supply terminal (12), wherein a first electrode of the storage capacitor (17) is coupled to a control terminal of the driver transistor (16), wherein the switching transistor (30) is designed to switch on and off a current flow (IL) through the light-emitting semiconductor device (13), wherein a first electrode of the control capacitor (34) is connected to a control terminal of the output transistor (33), wherein a second electrode of the control capacitor (34) is coupled to the first supply terminal (11), wherein a first terminal of the output transistor (33) is connected to a control terminal of the switching transistor (30), wherein the control capacitor (34) couples the control terminal of the output transistor (33) to a second terminal of the output transistor (33), and wherein the control resistor (36) is coupled to the first electrode of the control capacitor (34) and to a second electrode of the control capacitor (34).

The invention belongs to the technical field of circuit design, and provides a GOA circuit with an optimized structure, which comprises a plurality of cascaded circuit units, the circuit unit comprises write-in amp connected in sequence; the device comprises a shift module, a low-level stabilization module, a low-level maintenance output module, a pulse output module and a pulse output control module. According to the invention, the first to eighth transistors and the tenth transistor are replaced by LTPS-PMOS transistors, so that the mobility and output driving force of the circuit are improved, and in addition, the layout area is saved by adopting a smaller transistor design; through the designed five modules, electronic components of the whole circuit are reduced, the layout space is saved, and a narrower frame design is realized.