3 results about "Transistor design" patented technology

A light-emitting display device according to one or more embodiments of the present disclosure can comprise a display panel with multiple subpixels connected by data lines, gate lines, and gate drive voltage lines, a data drive circuit designed to supply data signals to the data lines, and a gate drive circuit designed to supply sampling signals to the gate lines, wherein each of the multiple subpixels comprises a light-emitting device, a drive transistor designed to connect between the gate drive voltage line and the light-emitting device and to control a current flowing through the light-emitting device, a first switching transistor designed to connect between a first node of the drive transistor and the data line, and a second switching transistor designed tobetween a second node of the drive transistor, which is connected to the light-emitting device, and the data line, may include a first capacitor connected between the first node and the second node, and a second capacitor connected between a third node of the drive transistor, which is connected to the drive voltage line, and the second node.

The invention relates to insulated gate bipolar transistor designs and methods. An insulated gate bipolar transistor includes a plurality of semiconductor layers, a trench material, an electrically insulating layer, and an emitter conductive layer. The semiconductor layer has (i) a semiconductor surface and (ii) a plurality of gate trenches and a plurality of emitter trenches formed through the semiconductor surface separated by a plurality of mesas. The trench material is disposed in the emitter trenches. The electrically insulating layer is formed over the semiconductor layers. The electrically insulating layer defines a plurality of openings aligned with the mesas and extending across the emitter trenches. The electrically insulating layer does not extend into the emitter trenches. The emitter conductive layer is formed over the electrically insulating layer. The emitter conductive layer directly contacts (i) each mesa and (ii) the trench material in each emitter trench through the openings. The emitter conductivity also extends across the emitter trenches.

Method for operating a semiconductor device, comprising: - Accessing the semiconductor device, which contains multi-stage storage transistors arranged in rows and columns, wherein the multi-stage storage transistors include silicon-oxide-nitride-oxide-silicon (SONOS)-based charge-trapping transistors designed to store one of N x analog values ​​corresponding to the N levels of a threshold voltage, VT, and a drain current, ID, where N is a natural number greater than 2; - Selecting at least one of the multi-stage storage transistors for a write operation to a setpoint, wherein the setpoint is one of the N x analog values ​​and corresponds to a setpoint ID range extending from a setpoint ID lower bound, LL, to a setpoint ID upper bound, UL;- Performing a partial programming operation on the at least one of the multi-stage storage transistors for ID level reduction, wherein the partial programming operation comprises at least one soft programming operation and one padding programming operation, wherein the partial programming operation is designed to reduce the ID level and increase a VT level for the at least one of the multi-stage storage transistors, and wherein multi-stage storage transistors not selected for the partial programming operation are disabled, wherein an initial check read is performed after the partial programming operation to determine how a reduced ID level compares to a target ID mean;- Performing a partial erase operation on at least one of the multi-stage storage transistors to raise the ID level, wherein the partial erase operation comprises at least one of a soft erase operation, a selective soft erase operation, and an annealing erase operation, wherein the partial erase operation is designed to raise the ID level and decrease the VT level for at least one of the multi-stage storage transistors, and wherein multi-stage storage transistors not selected for the selective soft erase operation are disabled, wherein a second check read is performed after the partial erase operation to determine how a raised ID level compares to the target ID mean; and - Determining that the write operation to the target value is complete when the ID level of the at least one of the multi-stage storage transistors falls within the target ID range.