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Analog probability AND gate circuit designed by CMOS transistor

A transistor and gate circuit technology, applied in the field of signal and information processing and integrated circuit design, can solve the problems of complex circuit design, easy to be interfered by noise, inaccurate and so on

Inactive Publication Date: 2009-04-08
杨曙辉
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] In general, analog circuits are sensitive to transistor deviation, susceptible to noise, affected by temperature, and complex in circuit design
However, if the nonlinearity of transistors is fully utilized, the overall accuracy can be achieved through system design, while the inaccuracy of local or individual transistors does not affect the accuracy of the entire circuit.

Method used

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  • Analog probability AND gate circuit designed by CMOS transistor
  • Analog probability AND gate circuit designed by CMOS transistor
  • Analog probability AND gate circuit designed by CMOS transistor

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Embodiment Construction

[0012] The purpose of the present invention is achieved through the following technical solutions: mainly composed of current input, output circuit and analog multiplier circuit. The input and output current values ​​are used to represent the input and output probability values, and the calculation of probability is realized through different structural forms of the circuit. Using MOS transistors, the current input circuit representing the A and B circuits, the current output circuit representing the F circuit, and the analog circuit for probability and calculation using the current value are designed. Functionally, the output probability value is the AND result of the two input probability values.

[0013] The advantages of the present invention are:

[0014] 1. The MOS tube of the analog multiplier unit works in a sub-threshold state, and the voltage and current have an exponential characteristic similar to that of a bipolar transistor. The circuit structure for realizing ...

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Abstract

The invention discloses a probability simulation AND gate circuit which is designed by utilizing a CMOS transistor and mainly consists of a current mirror circuit and an analog multiplier circuit. The AND calculation on the probability is realized by different structure modes of the circuit and by using the input and output current values to represent the input and output probability values; the probability simulation AND gate circuit can be applied to the calculation on an electronic NN and the channel decoding calculation in the digital communication field, thus leading the calculation to be improved by two orders of magnitude than the traditional digital logic gate circuit on the aspects of speed and power consumption. The circuit is a modular circuit and can be broadly applied to biology, digital communication and other chip designs which need probability simulation.

Description

[0001] The invention relates to a probability calculation circuit applied in integrated circuit design, in particular to an analog probability AND gate circuit designed by using CMOS transistors. technical field [0002] The invention relates to the fields of signal and information processing and integrated circuit design. Background technique [0003] In digital communication systems, in order to overcome channel interference, error correction code codecs are generally used. From a mathematical point of view, there are two ways of decoding error-correcting codes: algebraic decoding and probability decoding. In terms of circuit realization form, digital circuits are generally used to realize error correction code decoders. Digital circuits work well with algebraic decoding, but probabilistic decoding is more complex to implement with digital circuits. [0004] Using analog circuits to realize the decoding of error-correcting codes is based on probabilistic decoding algorit...

Claims

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Application Information

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IPC IPC(8): H03K19/20H03K19/0948H03M13/00
Inventor 杨曙辉
Owner 杨曙辉
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