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DDR storage adapter

a technology of ddr storage and ddr specifications, which is applied in the direction of memory architecture accessing/allocation, instruments, computing, etc., can solve the problem that storage technologies have not yet achieved a low-enough latency to render them compatible with ddr specifications

Active Publication Date: 2018-03-15
KIOXIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent describes a method for accessing a persistent memory over a memory interface, which includes allocating a virtual address range and generating a page fault when accessing virtual memory pages that don't have a corresponding physical page in the memory buffer. The method also includes mapping page table entries of virtual memory pages to physical pages of the memory buffer and transferring data between the two. The patent also discusses the use of eviction algorithms to select physical pages for eviction based on their recent usage. The technical effects of the patent include improving the latency of accessing persistent memory and optimizing data transfer between the memory buffer and the persistent memory.

Problems solved by technology

However, traditional physical block access storage devices such as HDDs and SSDs remain reliant on legacy communications interfaces, such as Serial AT Attachment (SATA) with the overhead of a storage software stack to perform input / output (I / O) operations.
However, these modern storage technologies have not yet achieved a low-enough latency to render them compatible with DDR specifications.
The latency overhead of the software stack that current OSs have in place to support block and file system access is disproportionate and acts as a significant performance penalty for these modern low-latency storage devices.

Method used

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Embodiment Construction

[0018]FIG. 1 is a block diagram of a host system 100, according to one embodiment of the invention. As shown in FIG. 1, host system 100 comprises a Central Processing Unit (CPU) 104 having a Memory Management Unit (MMU) 106. The MMU 106 is communicatively coupled to a plurality of DIMM connectors 108 (108a, 108b, 108c, and 108d) and is responsible for managing access to memory connected to the DIMM connectors 108. In one embodiment, the MMU 106 is communicatively coupled to the plurality of DIMM connectors 108 via a DDR-compliant interface. While only four DIMM connectors 108a, 108b, 108c, and 108d are shown in FIG. 1 for simplicity, in other embodiments, the number of DIMM connectors 108 may be one or more.

[0019]In one embodiment, one or more memory modules may be connected to the DIMM connectors 108a, 108b, 108c, or 108d. The memory modules may comprise any suitable memory devices, including DRAM, static random-access memory (SRAM), magnetoresistive random-access memory (MRAM), or...

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Abstract

A method of accessing a persistent memory over a memory interface is disclosed. In one embodiment, the method includes allocating a virtual address range comprising virtual memory pages to be associated with physical pages of a memory buffer and marking each page table entry associated with the virtual address range as not having a corresponding one of the physical pages of the memory buffer. The method further includes generating a page fault when one or more of the virtual memory pages within the virtual address range is accessed and mapping page table entries of the virtual memory pages to the physical pages of the memory buffer. The method further includes transferring data between a physical page of the persistent memory and one of the physical pages of the memory buffer mapped to a corresponding one of the virtual memory pages.

Description

FIELD OF THE INVENTION[0001]The present invention generally relates to adapting storage technologies to the Double Data Rate (DDR) memory interface that are not intrinsically compatible.BACKGROUND OF THE INVENTION[0002]Today, operating systems (OSs) provide software mechanisms to allow virtual memory backed by traditional physical block access storage devices such as hard disk drives (HDDs) and solid state drives (SSDs). These mechanisms allow for expanded application memory availability by making the available physical dynamic random-access memory (DRAM) of a host system act as a cache for a much larger traditional physical block access storage device (i.e. HDDs or SSDs). However, traditional physical block access storage devices such as HDDs and SSDs remain reliant on legacy communications interfaces, such as Serial AT Attachment (SATA) with the overhead of a storage software stack to perform input / output (I / O) operations.[0003]Modern storage technologies can produce storage devic...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F12/1009G06F12/1045G06F12/122G06F12/128
CPCG06F2212/70G06F12/1009G06F12/1045G06F2212/65G06F12/128G06F12/122
Inventor MAXEY, DAVID STANLEYKAMATH, NIDISH RAMACHANDRAAGRAWAL, VIKAS KUMAR
Owner KIOXIA CORP