43results about "Virtual memory details" patented technology

The disclosure discloses a memory space expansion method and apparatus, and an electronic device and a computer-readable storage medium, which are applied to a server. The method includes: receiving an access instruction configured with a virtual address, and querying whether there is a page table entry corresponding to the virtual address in a local page table and a remote page table; in response to the page table entry corresponding to the virtual address being not existed in the local page table and the remote page table, determining whether there is an unallocated physical address in the server; and in response to the unallocated physical address being not existed in the server, creating, on the basis of the physical address in a remote memory array apparatus, a remote memory page table entry corresponding to the virtual address.

A translation table entry load / store operation is performed for at least one target translation table entry address selected according to software defined address information identifying a selected address in the input address space. Each target translation table entry address includes an address of a leaf translation table entry providing address mapping information for translating the selected address from the input address space to an output address space or an address of a branch translation table entry traversed in a translation table roaming operation for obtaining the leaf translation table entry. For a given target conversion table entry of the at least one target conversion table entry, at least one variant of the translation table entry load / store operation supports clearing access trace metadata of the given target translation table entry from a first state indicating that at least one load / store access to a corresponding region of the input address space has occurred to a second state indicating that load / store access to the corresponding region has not occurred.

A coarse-grained reconfigurable processor (CGRP) system for implementing data-parallel training of a neural network is presented. The CGRP system includes a set of coarse-grained reconfigurable units (CGRUs) in a first CGRP configured to implement at least a portion of the neural network, to determine first and second gradients, respectively, of first and second model parameters based on a batch of training data, and to store the first and second gradients in a memory, a network interface including an external direct memory access (DMA) engine coupled between the memory and a network, and a work queue associated with the external DMA engine, wherein completion of determining the first gradient triggers a first work queue entry of the work queue that directs the external DMA engine to transfer the first gradient from the memory over the network to another memory coupled to a second CGRP for a gradient reduction operation.

A translation table entry load / store operation is performed for at least one target translation table entry address selected depending on software-defined address information identifying a selected address in an input address space. Each target translation table entry address comprises an address of a leaf translation table entry providing address mapping information for translating the selected address from the input address space to an output address space or an address of a branch translation table entry traversed in a translation table walk operation for obtaining that leaf translation table entry. At least one variant of the translation table entry load / store operation supports, for a given target translation table entry of the at least one target translation table entry, clearing access tracking metadata of the given target translation table entry from a first state (indicating that at least one load / store access has occurred to a corresponding region of input address space) to a second state (indicating that no load / store accesses have occurred to the corresponding region).

A transaction manager for use with memory is described. The transaction manager can include a write data buffer to store outstanding write requests, a read data multiplexer to select between data read from the memory and the write data buffer, a command queue and a priority queue to store requests for the memory, and a transaction table to track outstanding write requests, each write request associated with a state that is Invalid, Modified, or Forwarded.

A coarse-grained reconfigurable processor (CGRP) system. The CGRP system includes a set of coarse-grained reconfigurable units (CGRUs) in a first coarse-grained reconfigurable processor that is coupled to a first memory, a network interface including an external direct memory access (DMA) engine coupled to the first memory, and a work queue associated with the external DMA engine.

Techniques of a system operable to allocate physical pages of memory are described. The system may include a memory - side cache, a memory - side cache monitoring unit coupled to the memory - side cache, and an operating system (OS) page allocator. The OS page allocator may receive feedback from the memory - side cache monitoring unit. The OS page allocator may adjust a page allocation policy based on the feedback received from the memory - side cache monitoring unit, where the page allocation policy defines the physical pages allocated by the OS page allocator.

A method and system for user authentication by using an authentication virtual code are provided. A user authentication method using an authentication virtual code includes receiving, by a server, the authentication virtual code, searching, by the server, for an authentication card storage location, at which the authentication card is registered, in a storage location search algorithm based on the authentication virtual code, identifying, by the server, a user by extracting user information stored after being matched with the found authentication card storage location, verifying, by the server, an authentication virtual code based on a time point at which the authentication virtual code is received, and approving, by the server, user authentication.

Methods, systems, and devices for memory with a virtual page size are described. Memory cells may be accessed in portions or page sizes that are tailored to a particular use or application. A variable page size may be defined that represents a subset or superset of memory cells in a nominal page size for the array. For example, memory cells associated with a page size of a memory array may be accessed with commands to a memory array. Each command may contain a particular addressing scheme based on the page size of the memory array and may activate one or more sets of memory cells within the array. The addressing scheme may be modified based on the page size of the memory array. Upon activating a desired set of memory cells, one or more individual activated cells may be accessed.

Systems, apparatus, and methods for direct memory access. A system direct memory access (SDMA) device disposed on a processor die sends a message to a data structure device, the message including the physical addresses of a source buffer and a destination buffer, and the size of a data transfer. The data structure device sends an instruction to a first proxy device, the instruction including the physical addresses of the source buffer and the destination buffer, and the size of the data transfer. Each of the first proxy devices reads a portion of the source buffer from a memory device at the physical address of the source buffer. Each of the first proxy devices sends the portion of the source buffer to one of the second proxy devices. Each of the second proxy devices writes the portion of the source buffer to the destination buffer.

Method for operating an access to a cache memory via an effective address, comprising a tag field and a cache row index field, wherein the cache memory comprises a primary cache directory that is logically addressed and logically tagged, wherein the method comprises: Determine (501) a first group of bits and a second group of bits of the marker field; Providing a record index that is logically indexed using row index bits of the cache row index field and logically marked using the first group of bits; Providing a validation directory that is logically indexed using the row index bits and set bits, and logically marked using the second group of bits; a first search (503) for the row index bits and the first group of bits of the effective address in the record directory and generating a record identifier that indicates the record containing the respective cache row of the effective address; second search (505) for the record identifier, the row index bits and the second group of bits of the effective address in the validation directory; as a response to the detection of the presence of the cache line in the sentence based on the second search, generating (507) a hit signal.

A system having: a compute express link fabric; a plurality of memory devices having random access memory cells, a memory bus; a main memory; at least one processing device connected to the main memory via the memory bus, and connected to the compute express link fabric; a peripheral bus; and a plurality of memory sub-systems connected to the at least one processing device via the peripheral bus. A plurality of portions of the random access memory cells in the plurality of memory devices are allocated respectively as a plurality of host memory buffers for the plurality of memory sub-systems. Each memory buffer can have random access memory cells allocated from more than one of the memory devices.

A storage device and an operating method of the storage device are provided. The storage device comprises a non-volatile memory including a virtual block including an L2P pair region storing a pair of a logical page number (LPN) and a physical page number (PPN) (LPN-PPN pair) and a data region storing data addressed to the PPN, a volatile memory including an L2V table storing a virtual block number (VBN) corresponding to the LPN, an L2P cache storing the LPN-PPN pair, and an LPN range map storing a portion of the LPN stored in the L2P pair region of the virtual block, and a controller configured to control the non-volatile memory and the volatile memory.

A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: store a namespace map mapping blocks of logical block addresses in a namespace to blocks from a logical address capacity of the non-volatile storage media; adjust the namespace map to change the size of the namespace; and translate logical addresses in the namespace to physical addresses for the non-volatile storage media using the namespace map.

A processor core (215) associated with a first cache (205) begins to enter a powered-down state. In response, information representing a set of entries (220) of the first cache is stored in a retention area (230), the retention area receiving a retention voltage while the processor core is in the powered-down state. Information indicating one or more failed entries in the set of entries is also stored in the retention area. In response to the processor core beginning to exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one failed entry.

The translation table entry load / store operation is performed on at least one target translation table entry address selected depending on software-defined address information identifying a selected address in the input address space. Each target translation table entry address includes an address of a leaf translation table entry that provides address mapping information for translating the selected address from the input address space to the output address space, or an address of a branch translation table entry that is traversed in a translation table walk operation to obtain the leaf translation table entry. At least one variant of the translation table entry load / store operation supports, for a given target translation table entry of the at least one target translation table entry, clearing access tracking metadata of the given target translation table entry from a first state (indicating that at least one load / store access has occurred to the corresponding region of the input address space) to a second state (indicating that no load / store access has occurred to the corresponding region).

Apparatuses, systems, and techniques to manage memory arrays. In at least one embodiment an application programming interface (API) is performed to disassociate a virtual address indicated by the API from a corresponding physical address.

Examples described herein relate to a network interface device comprising circuitry to receive an access request with a target logical block address (LBA) and based on a target media of the access request storing at least one object, translate the target LBA to an address and access content in the target media based on the address. In some examples, translate the target LBA to an address includes access a translation entry that maps the LBA to one or more of: a physical address or a virtual address. In some examples, translate the target LBA to an address comprises: request a software defined storage (SDS) stack to provide a translation of the LBA to one or more of: a physical address or a virtual address and store the translation into a mapping table for access by the circuitry. In some examples, at least one entry that maps the LBA to one or more of: a physical address or a virtual address is received before receipt of an access request.

A transaction manager for use with memory is described. The transaction manager can include a write data buffer to store outstanding write requests, a read data multiplexer to select between data read from the memory and the write data buffer, a command queue and a priority queue to store requests for the memory, and a transaction table to track outstanding write requests, each write request associated with a state that is Invalid, Modified, or Forwarded.

A processor core (215) associated with a first cache (205) initiates entry into a powered-down state. In response, information representing a set of entries (220) of the first cache are stored in a retention region (230) that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.

Method for performing a data prefetch from a cache memory, wherein the method is performed by a root complex compliant with a Peripheral Component Interconnect Express (PCIe) protocol, and wherein the method comprises: Receiving a data packet (502) from a device connected to the root complex via a PCIe-compliant connection; Identify a memory transaction hint bit (506) based on the received data packet; Determining a memory transaction using the memory transaction indicator bit; and Performing an optimization process based at least in part on the specified memory transaction (508), wherein performing the optimization process (508) includes performing a caching behavior optimization process and wherein the caching behavior optimization process includes performing an advance retrieval of ownership in response to the memory transaction hint indicating a streaming write operation.

A storage device and an operating method of the storage device are provided. The storage device includes a non-volatile memory including a virtual block including an L2P pair region storing a pair of logical page number (LPN) and physical page number (PPN) (LPN-PPN pair), and a data region storing data addressed to the PPN; a volatile memory including an L2V table storing a virtual block number (VBN) corresponding to the LPN, an L2P cache storing the LPN-PPN pair, and an LPN range map storing a portion of the LPN stored in an L2P pair region of a virtual block; and a controller configured to control the non-volatile memory and the volatile memory.

A system having: a computer express link fabric; a plurality of memory devices having random access memory cells, a memory bus; a main memory; at least one processing device connected to the main memory via the memory bus, and connected to the computer express link fabric; a peripheral bus; and a plurality of memory sub-systems connected to the at least one processing device via the peripheral bus. A plurality of portions of the random access memory cells in the plurality of memory devices are allocated respectively as a plurality of host memory buffers for the plurality of memory sub-systems. Each memory buffer can have random access memory cells allocate from more than one of the memory devices.

The embodiment of the present application discloses a memory allocation method and a computing device, which is applied to a computing device of an ARM architecture; the method includes: configuring the page size of a first virtual page of a first virtual address space, and the page size of a second virtual page of a second virtual address space, wherein the page size of the first virtual page is larger than the page size of the second virtual page; determining whether the task to be allocated memory belongs to a preset control group; if the task belongs to the preset control group, allocating the first virtual page or the second virtual page to the task based on the control group to which the task belongs. By configuring the first virtual address space and the second virtual address space with different page size granularities, and allocating the first virtual page or the second virtual page to different tasks based on the preset control group, memory allocation with different page size granularities can be implemented under an ARM architecture server, meeting the more diverse and flexible memory allocation requirements of an ARM architecture server.

Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Systems and methods related to processors with descriptor table instruction circuitry are disclosed herein. A processor may be defined by an instruction set including an instruction. The processor may comprise: a set of data structures stored in a memory, a configuration register storing a set of characteristics of the set of data structures, and circuitry configured to execute an instruction having a syntax that includes an address in an address space of the data structures. Execution of the instruction may include using the address in the address space of the data structures and the information stored in the configuration register to calculate an address in the address space of the memory. This alleviates the burden of programming a computation in that the address space of the data structures is a step closer to the application level of the computation.

A computer system is presented. The computer system comprises a memory system that stores data, a computer processor, and a memory access engine. The memory access engine is configured to: receive a first instruction of a computing process from the computer processor, wherein the first instruction is for accessing the data from the memory system; acquire at least a part of the data from the memory system based on the first instruction; and after the acquisition of the at least a first part of the data, transmit an indication to the computer processor to enable the computer processor to execute a second instruction of the computing process.

According to the embodiments, a nonvolatile memory device is configured to store a normal operating system, and store a bootloader. A host device is capable of initiating the normal operating system by using the bootloader. The host device is configured to determine whether a first condition is established based on information obtained from the nonvolatile memory device; and rewrite, when determined the first condition is established, the bootloader so that an emergency software is initiated when booting the host device. The emergency software is executed on the host device. The host device is capable of issuing only a read command to the nonvolatile memory device under a control of the emergency software.

A storage device and an operating method of the storage device are provided. The storage device comprises a non-volatile memory including a virtual block including an L2P pair region storing a pair of a logical page number (LPN) and a physical page number (PPN) (LPN-PPN pair) and a data region storing data addressed to the PPN, a volatile memory including an L2V table storing a virtual block number (VBN) corresponding to the LPN, an L2P cache storing the LPN-PPN pair, and an LPN range map storing a portion of the LPN stored in the L2P pair region of the virtual block, and a controller configured to control the non-volatile memory and the volatile memory.

A data processing apparatus comprises: branch prediction circuitry adapted to store at least one branch prediction state entry associated with an instruction stream; input circuitry adapted to receive at least one input to generate a new branch prediction state entry, wherein the at least one input comprises a plurality of bits; and encoding circuitry adapted to perform an encoding operation to encode at least some of the plurality of bits based on a value associated with a current execution environment in which the instruction stream is being executed. This prevents potential attacks that exploit the ability of branch prediction entries trained by one execution environment to be used as a basis for branch prediction by another execution environment.