15results about "Virtual memory details" patented technology

A coarse-grained reconfigurable processor (CGRP) system. The CGRP system includes a set of coarse-grained reconfigurable units (CGRUs) in a first coarse-grained reconfigurable processor that is coupled to a first memory, a network interface including an external direct memory access (DMA) engine coupled to the first memory, and a work queue associated with the external DMA engine.

A method and system for user authentication by using an authentication virtual code are provided. A user authentication method using an authentication virtual code includes receiving, by a server, the authentication virtual code, searching, by the server, for an authentication card storage location, at which the authentication card is registered, in a storage location search algorithm based on the authentication virtual code, identifying, by the server, a user by extracting user information stored after being matched with the found authentication card storage location, verifying, by the server, an authentication virtual code based on a time point at which the authentication virtual code is received, and approving, by the server, user authentication.

Methods, systems, and devices for memory with a virtual page size are described. Memory cells may be accessed in portions or page sizes that are tailored to a particular use or application. A variable page size may be defined that represents a subset or superset of memory cells in a nominal page size for the array. For example, memory cells associated with a page size of a memory array may be accessed with commands to a memory array. Each command may contain a particular addressing scheme based on the page size of the memory array and may activate one or more sets of memory cells within the array. The addressing scheme may be modified based on the page size of the memory array. Upon activating a desired set of memory cells, one or more individual activated cells may be accessed.

Systems, apparatus, and methods for direct memory access. A system direct memory access (SDMA) device disposed on a processor die sends a message to a data structure device, the message including the physical addresses of a source buffer and a destination buffer, and the size of a data transfer. The data structure device sends an instruction to a first proxy device, the instruction including the physical addresses of the source buffer and the destination buffer, and the size of the data transfer. Each of the first proxy devices reads a portion of the source buffer from a memory device at the physical address of the source buffer. Each of the first proxy devices sends the portion of the source buffer to one of the second proxy devices. Each of the second proxy devices writes the portion of the source buffer to the destination buffer.

A system having: a compute express link fabric; a plurality of memory devices having random access memory cells, a memory bus; a main memory; at least one processing device connected to the main memory via the memory bus, and connected to the compute express link fabric; a peripheral bus; and a plurality of memory sub-systems connected to the at least one processing device via the peripheral bus. A plurality of portions of the random access memory cells in the plurality of memory devices are allocated respectively as a plurality of host memory buffers for the plurality of memory sub-systems. Each memory buffer can have random access memory cells allocated from more than one of the memory devices.

A storage device and an operating method of the storage device are provided. The storage device comprises a non-volatile memory including a virtual block including an L2P pair region storing a pair of a logical page number (LPN) and a physical page number (PPN) (LPN-PPN pair) and a data region storing data addressed to the PPN, a volatile memory including an L2V table storing a virtual block number (VBN) corresponding to the LPN, an L2P cache storing the LPN-PPN pair, and an LPN range map storing a portion of the LPN stored in the L2P pair region of the virtual block, and a controller configured to control the non-volatile memory and the volatile memory.

The translation table entry load / store operation is performed on at least one target translation table entry address selected depending on software-defined address information identifying a selected address in the input address space. Each target translation table entry address includes an address of a leaf translation table entry that provides address mapping information for translating the selected address from the input address space to the output address space, or an address of a branch translation table entry that is traversed in a translation table walk operation to obtain the leaf translation table entry. At least one variant of the translation table entry load / store operation supports, for a given target translation table entry of the at least one target translation table entry, clearing access tracking metadata of the given target translation table entry from a first state (indicating that at least one load / store access has occurred to the corresponding region of the input address space) to a second state (indicating that no load / store access has occurred to the corresponding region).

Apparatuses, systems, and techniques to manage memory arrays. In at least one embodiment an application programming interface (API) is performed to disassociate a virtual address indicated by the API from a corresponding physical address.

A system having: a computer express link fabric; a plurality of memory devices having random access memory cells, a memory bus; a main memory; at least one processing device connected to the main memory via the memory bus, and connected to the computer express link fabric; a peripheral bus; and a plurality of memory sub-systems connected to the at least one processing device via the peripheral bus. A plurality of portions of the random access memory cells in the plurality of memory devices are allocated respectively as a plurality of host memory buffers for the plurality of memory sub-systems. Each memory buffer can have random access memory cells allocate from more than one of the memory devices.

Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Systems and methods related to processors with descriptor table instruction circuitry are disclosed herein. A processor may be defined by an instruction set including an instruction. The processor may comprise: a set of data structures stored in a memory, a configuration register storing a set of characteristics of the set of data structures, and circuitry configured to execute an instruction having a syntax that includes an address in an address space of the data structures. Execution of the instruction may include using the address in the address space of the data structures and the information stored in the configuration register to calculate an address in the address space of the memory. This alleviates the burden of programming a computation in that the address space of the data structures is a step closer to the application level of the computation.

Processor (870, 880), including the following: multiple cores (1210, 1211) to execute instructions and process data; one or more translation buffers, TLBs, (1220), comprising multiple entries to accommodate address translations from virtual to physical, which are usable by at least one of the multiple cores (1210, 1211) when executing instructions; a page table entry, PTE, invalidation circuit (1214) to execute a PTE invalidation instruction on a first core to invalidate a first PTE in TLBs (1220) of other cores, wherein the PTE invalidation circuit (1214), in response to an execution of the PTE invalidation instruction, determines a number of other TLBs (1220) of other cores which need to be notified of the PTE invalidation, transmits PTE invalidation messages to the other TLBs (1220) and waits for replies; a lock-switching complex to allow a thread to lock the first PTE in the first TLB (1220) to ensure that only one thread can modify the first PTE at any given time, wherein the first TLB (1220) serves to modify the first PTE when the thread acquires the lock, and wherein the lock-switching complex releases the lock on the first PTE in response to receiving replies from all the other TLBs (1220), wherein each TLB (1220) includes a PTE invalidation request treatment circuit complex (1221) to receive invalidation requests transmitted from other TLBs (1220), wherein the invalidation request treatment circuit complex (1221) in response causes the TLBs (1220) to invalidate one or more PTEs identified in the invalidation requests and transmits a reply indicating the invalidation; and a PTE invalidation sequence control circuit (1224) which is to be programmed with a counter value initially set to the number of other TLBs (1220) which need to be notified, wherein the PTE invalidation sequence control circuit (1224) decrements the counter value upon receiving each reply from each of the other TLBs (1220), wherein the blocking circuit complex releases the block when the counter value has been decremented to a threshold value.

A total number V of virtual host-managed device memory (HDM) decoder configurations are generated for the same total number V of HDM memory regions attached to a non-host computing device. Each virtual HDM decoder configuration in the virtual HDM decoder configurations corresponds to a respective HDM memory region in the HDM memory regions. A proper subset of one or more virtual HDM decoder configurations is selected from among the virtual HDM decoder configurations to configure one or more physical HDM decoders of a total number P of the non-host computing device into one or more virtual HDM decoders. The one or more physical HDM decoders configured as one or more virtual HDM decoders are applied to translate a host physical address (HPA) received from a host computing device in a memory access transaction involving the host computing device and the non-host computing device.

Machine-accessible storage medium(s) containing code stored thereon, wherein the code, when executed on a machine, causes the machine to: determined that at least one first device is connected to a first of a plurality of ports of a root complex (615) of a system, assigns addresses that correspond to a first hierarchy (620) of facilities that include the first facility, determined that a second facility is connected via a mapping portal bridge (705) to a second of the multiple connections of the root complex (615) and that the second facility is contained in another, second hierarchy (625) of facilities, and triggers the creation of a mapping table (1015) corresponding to the mapping portal bridge (705), wherein the mapping table (1015) corresponds to a translation between an addressing used in a first view of a configuration address space of the system and an addressing used in a second view of the configuration address space, wherein the first view comprises a view of the root complex (615) and the second view comprises a view corresponding to the second setup hierarchy and the addresses (1110) assigned to the first setup hierarchy correspond to the first view, wherein the creation of the mapping table (1015) includes a speculative mapping between the addressing used in the first view of the configuration address space and the addressing used in the second view of the configuration address space, wherein the speculative mapping includes the following: Inserting a first value from a numbering queue (1010), where the first value represents an address of the second hierarchy (625) of facilities, Identification of a second value, where the second value represents an address of the second hierarchy (625) of facilities, by removal from the numbering queue (1010); and Mapping the second value to an address in the first hierarchy of institutions.

Various embodiments generally relate to techniques for shared virtual memory (SVM) access protection, e.g., such as by performing a security check whenever a write request arrives from a SVM device. Some embodiments particularly relate to an input / output memory management unit (IOMMU) that prevents a SVM device from modifying a code page as a result of a memory transaction request by generating an access request fault and / or a translation complete with read-only access in response to the memory transaction request.