Sub word line driver of semiconductor memory device

Abstract

A layout structure of a sub word line of a semiconductor memory device is disclosed. A sub word line driver of a semiconductor memory device includes: a plurality of first active regions arranged in a line shape in a first direction; a plurality of second active regions spaced apart from the plurality of first active regions a predetermined distance in a second direction, and arranged in a line shape in the first direction; a first main word line disposed over the first active regions, and formed in a diagonal direction in the first active regions; a second main word line disposed over the second active regions, and formed in a diagonal direction in the second active regions; and a pickup active region disposed between the first main word line and the second main word line.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application No. 10-2016-0179757 filed on Dec. 27, 2016, the disclosure of which is hereby incorporated by reference in its entirety.BACKGROUND OF THE INVENTION1. Technical Field[0002]Embodiments of the present disclosure relate to a sub word line driver of a semiconductor memory device, and more particularly to a layout of forming a well pickup in a PMOS region of a sub word line driver.2. Related Art[0003]Generally, a semiconductor memory device includes a plurality of memory cells and a circuit for controlling the memory cells.[0004]FIG. 1 is a conceptual diagram illustrating an arrangement structure of cell mats MATs for use in a general semiconductor memory device.[0005]Referring to FIG. 1, the semiconductor memory device includes a plurality of mats MATs, each of which includes array-shaped memory cells for storing data. Each mat MAT may include a bit-li...

AI Technical Summary

Benefits of technology

The present disclosure is about a way to improve the structure of a sub word line to prevent it from taking up too much space. This results in the creation of a well pickup active region in a PMOS region. This can lead to improved efficiency and a smaller footprint of the sub word line driver.

Problems solved by technology

However, the conventional art has difficulty in forming a well pickup active region in a PMOS region while simultaneously reducing the region of a sub word line driver, such that the conventional art unavoidably shares well pickup active regions of the other regions.

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