Quantization noise cancellation for fractional-n phased-locked loop

Abstract

A system includes an oscillator, a frequency divider, and a delay circuit. The oscillator may generate a clock signal using a reference signal. A frequency of the clock signal may be a non-integer multiple of a frequency of the reference signal. The frequency divider may generate a feedback signal using the clock signal and an adjustment factor based on the non-integer multiple. The delay circuit may select a particular delayed feedback signal from a plurality of delayed feedback signals based on a value of the adjustment factor. Each of the delayed feedback signals may be generated using periods of the clock signal. The delay circuit may also modify the particular delayed feedback signal using a portion of a period of the clock signal based on the adjustment factor. The oscillator may also adjust the frequency of the clock signal using the reference signal and the particular delayed feedback signal.

Description

BACKGROUNDTechnical Field[0001]Embodiments described herein are related to the field of integrated circuit implementation, and more particularly to the implementation of frequency synthesizer circuits.Description of the Related Art[0002]Systems-on-a-chip (SoCs) designs and wireless transceiver systems may include multiple frequency synthesizer clock generation modules, configured to output a clock signal at a target frequency or to modulate a carrier signal using frequency modulation (FM) / phase modulation (PM) encoding. Frequency synthesizer circuits may utilize a reference clock to generate output clock signals of a different frequency than the reference clock. In some embodiments, the target frequency may be programmable, allowing a processor in the SoC to adjust the clock frequency to an optimum value for current operating conditions, e.g., set a low frequency value to conserve power when fewer tasks are active, or vice versa. Some examples of such closed-loop clock generators in...

AI Technical Summary

Benefits of technology

The patent describes a clock generation unit that includes an oscillator circuit, a frequency divider circuit, and a delay circuit. The system generates a clock signal with a variable frequency based on an input signal. The frequency divider circuit adjusts the clock signal based on an adjustment factor to create a feedback signal. The delay circuit selects a particular delayed feedback signal based on the adjustment factor. The oscillator circuit adjusts the frequency of the clock signal based on the reference signal and the selected delayed feedback signal. The delay circuit can also calibrate the portion of the clock signal based on the adjustment factor. The technical effect of this invention is to provide a more precise and accurate clock signal for various applications such as communication devices and electronic devices.

Problems solved by technology

In a fractional-N PLL, the switching between divisor values may cause quantization noise in the generated output clock signal.

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