Routing and control protocol for high-performance interconnect fabrics

Abstract

Operating a computer network uses a routing and control protocol, the computer network having an interconnect fabric including routing and control distribution devices and fabric interface devices, each of the routing and control distribution devices and each of the fabric interface devices having a state machine having an input processing unit having parallel input buffers, an output processing unit having parallel output buffers and an arbiter; operating the state machine based on a set of instructions and a table located at the state machine; transferring data from the input processing unit to the output processing unit; choosing a highest priority currently flit occupied parallel input buffer located in the input processing unit for data transmission on a highest priority currently flit occupied channel; and; interrupting the highest currently flit occupied priority channel when one of the parallel input buffers is detected to contain a superseding even higher priority flit.

Description

CROSS REFERENCE TO RELATED APPLICATION[0001]This application claims the benefit of U.S. Provisional Application No. 62 / 687,785 filed on Jun. 20, 2018. This application claims the benefit of PCT / US2019 / 031052 filed on May 7, 2019, which claims priority to application Ser. No. 15 / 997,573, filed on Jun. 4, 2018. Each of the patent applications identified above is incorporated herein by reference in its entirety to provide continuity of disclosure.FIELD OF THE INVENTION[0002]The field of the invention includes parallel processors, sometimes called many-core. An example is a conventional parallel processor that splits the execution of a program among multiple processors.BACKGROUND OF THE INVENTION[0003]A problem with this parallel processing has been that the multiple processors need to be able to seamlessly communicate data and control signals. One unsatisfactory approach is a bus-based interconnect. For example, U.S. Pat. No. 7,376,295 to Lee, et al. describes opto-electronic processor...

AI Technical Summary

Benefits of technology

The disclosure describes a flow control protocol for a state machine that can switch between a default interrupt mode and a transient switching mode. In the default mode, the arbiter selects the highest priority flit for data transfer, but if there are higher priority flits that may interrupt the selected channel, the arbiter can switch to the transient mode to hold open a channel for the higher priority flits. This allows for seamless control with low latency. The protocol includes an interleave mechanism to insert a CRC code to temporarily hold open a channel until the desired data transfer is complete.

Problems solved by technology

A problem with this parallel processing has been that the multiple processors need to be able to seamlessly communicate data and control signals.

One unsatisfactory approach is a bus-based interconnect.

However, such an interconnect approach is not scalable beyond a modest number of processors and / or chips.

Other disadvantages of this approach have been relatively high cost, and when the scale increases sufficiently excessive bulk and even heat.

However, a disadvantage of this approach is that there are performance issues especially with regard to control and latency.

Heretofore, the requirement(s) of seamless communication, economy, compact form factor, energy efficiency while avoiding control and latency issues referred to above have not been fully met.

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