Memory device

Abstract

A memory device includes a memory array, a bit line driving circuit, a word line driving circuit, a read / write circuit, a controller, and a reference driving circuit. The memory array includes several memory units. The bit line driving circuit is configured to interpret a memory bit address and to drive a bit line. The word line driving circuit is configured to interpret a memory word address and to drive a word line. The read / write circuit is configured to read, set, or reset the memory units. The controller is configured to switch the memory array to work in a single memory unit mode or a dual memory unit mode. The reference driving circuit is configured to drive a reference line, wherein the reference line comprises several reference units, and the reference line and the reference units are located in the memory array.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims the priority benefit of Chinese Application serial no. 201811582708.7, filed Dec. 24, 2018, the full disclosure of which is incorporated herein by reference.TECHNICAL FIELD[0002]The present disclosure relates to a memory device. More particularly, the present disclosure relates to a phase change memory device.DESCRIPTION OF RELATED ART[0003]In memory technology, a resistive random-access memory includes a phase change memory (PCM), which can change a resistance value of a component by a crystal phase change of the material thereof, so as to store information by a change in resistance value. When the material in the memory element is crystalline, it exhibits a low resistance value, and conversely, when the material in the memory element is in an amorphous state, it exhibits a high resistance value, thereby storing data such as “1” or “0”.[0004]In the prior art, when reading the data of the memory unit in the memory d...

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Benefits of technology

[0008]In sum, embodiments of this disclosure are to provide a memory device, and in particular, a phase change memory device. After the chip is completed, the user is still able to adopt single memory unit mode or dual memory unit mode according to his own needs. When the memory is operated in the single memory unit mode, the memory may obtain the maximum design capacity; in addition, since the reference current is generated by using the reference resistor, and the reference resistor is formed by the same material and process of the resistive random-access element, therefore, the process variation mechanism of the reference resistor is the same as that of the resistive random-access element of the memory unit. Therefore, the resistance variation of the resistive random-access element may be almost the same as the variation of the process, which results in more reading accuracy than the prior art. When operating in the dual memory unit mode, the data stored in the dual memory unit is read to determine whether the data stored in the memory unit is “1” or “0” so as to increase the accuracy of the data of the memory unit. The dual memory operation mode eliminates the loading effect of the memory unit, thus improving the reading speed of the memory.

Problems solved by technology

However, comparisons with current values may cause errors due to different bias voltages.

Furthermore, the judgment of data reading with a single memory unit is liable to cause errors.

Existing memory architectures include at least two major problems: (1) the reference circuit is located in the read / write circuit, in which typically a transistor is configured to generate a reference current.

The position difference between the location of the transistor and the location of the memory cell is too large, and the magnitude of the currents generated at different positions of different memory cells are slightly different, which causes different noise margins for determining logic “1” or “0” of each cell and makes the optimization of memory performance be unreachable.

The process variation mechanism of the memory cell is different from that of the transistor, so the reference current cannot accurately adapt to the variation of the memory cell.

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