Delay locked loop

Abstract

Embodiments disclose a delay locked loop. The delay locked loop including a main delay circuit configured to generate initial clocks by delaying an internal clock, and sub-delay lines configured to generate phase clocks having a phase difference corresponding to a desired initial delay by respectively delaying the internal clock and the initial clocks. The phase difference among the phase clocks may be adjusted according to delay values of the sub-delay lines.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0058006 filed on May 17, 2019, which is incorporated herein by reference in its entirety.BACKGROUND1. Field[0002]Exemplary embodiments relate to a semiconductor device, and more particularly, to a delay locked loop suitable for use in a semiconductor device operating at a high speed.2. Discussion of the Related Art[0003]A semiconductor device may use a delay locked loop to compensate for time delays caused by internal circuits when an external clock is used internally.[0004]The delay locked loop generates multi-phase clocks by delaying an internal clock, compares a phase difference between the internal clock and a feedback clock, and performs a locking operation by adjusting a delay value on the basis of a result of the comparison. The delay value is the delay between successive phase clocks generated by the delay locked loop. However, an initia...

AI Technical Summary

Benefits of technology

This patent describes a delay locked loop that helps design high-speed semiconductor devices by solving problems with initial delay that limits their operating frequency. The delay locked loop uses delay values from sub-delay lines to adjust the phase difference among clocks and generate phase clocks that meet a condition that the phase difference is smaller than one cycle of the internal clock divided by the number of phase clocks. This reduces the limitations of initial delay and allows for operation at a desired frequency, resulting in faster semiconductor devices without frequency limitation.

Problems solved by technology

However, an initial value of the delay value of the delay locked loop may limit an operating frequency of the semiconductor device.

However, the delay locked loop according to the related art has a problem that the four phases will not be aligned within one cycle of the internal clock when the initial value of the delay value corresponds to a phase difference larger than 90° of the internal clock.

Such a problem of the initial value of the delay value may limit the overall operating speed of the semiconductor device operating at a high speed.

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