Communication device, and electronic device comprising same
a communication device and electronic device technology, applied in the direction of logic circuits, logic circuit coupling/interface arrangements, pulse techniques, etc., can solve the problems of high probability of error occurring and inability to achieve voltage levels of driving power
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first embodiment
[0085]FIG. 6 is a circuit diagram of a transmission circuit and a reception circuit according to a
[0086]Referring to FIG. 6, the first transmission circuit 131 of the first communication device 130 may include a first FET Q1, pull-up resistances R1 and R2 and a first LPF 135. In addition, the second reception circuit 141 of the second communication device 140 may include a second FET Q2, pull-up resistances R5 and R6, and a second LPF 145.
[0087]The first communication device 130 and the second communication device 140 may be designed so as to transmit and receive the high signal as a default even when there is no data transfer. This is based on the basic feature of the above-described UART communication.
[0088]Then, the operation of the first transmission circuit 131 and the second reception circuit 141 may be varied according to whether the input signal input to the first transmission circuit 131 is a high signal or a low signal.
[0089]Below, the operation of the first transmission c...
second embodiment
[0117]FIG. 7 is a circuit diagram of a transmission circuit and a reception circuit according to a
[0118]Referring to FIG. 7, the first transmission circuit 131 and the second reception circuit 141 may further include resistances R7 and R8 and TVS diodes D1 and D2.
[0119]The gate of the first FET Q1 and the resistance R7 connected to the first driving power and the gate of the second FET Q2 and the resistance R8 to be connected to the second driving power may prevent the destruction of element which may be generated by applying a sudden voltage to the gate of each FET.
[0120]The TVS diodes D1 and D2 may be connected to the output stage of the first transmission circuit 131 and the input stage of the second reception circuit 141. Then, the TVS diodes D1 and D2 may prevent an electrostatic discharge (ESD) which is temporarily generated by the signal input to each circuit.
[0121]FIG. 8 is a diagram illustrating an operation of a low pass filter (LPF) circuit according to an embodiment of t...
third embodiment
[0184]FIG. 11 is a circuit diagram illustrating a level shift according to a
[0185]Referring to FIG. 11, the operation of the first transmission circuit 131 and the second reception circuit 141 in case the second processor 120 operates at a voltage level greater than the first processor 110, and the plurality of power cannot be used in the first transmission circuit 131 may be confirmed.
[0186]The case of FIGS. 9 and 10 described above assume that the first transmission circuit 131 or the second reception circuit 141 are able to use the plurality of power. However, there may be a case where the first transmission circuit 131 or the second reception circuit 141 is not able to use the plurality of power at an actual implementation due to the type of the electronic device, the limitation of the related components, or the like.
[0187]The operation of the first transmission circuit 131 and the second reception circuit 141 in case the first processor 110 operates at a voltage level greater t...
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