Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation
a bipolar transistor and accumulation layer technology, applied in the field of semiconductor devices, can solve the problems of inability to scale down (less than 30 nm) easily without more advanced and expensive lithography technologies, and the thickness subcollector of conventional bipolar junction transistors (bjts) becomes incompatible with the integration of high-performance soi cmos devices, and achieves the effect of reducing substrate bias
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[0035]The present invention, which provides a vertical SOI BJT which uses a SOI layer with a back gate-induced accumulation layer as the subcollector located on regions of a second buried insulating region having a second thickness using a standard SOI starting wafer with a first buried insulating region having a first thickness and the method thereof, will now be described in greater detail by referring to the drawings that accompany the present application. The drawings are provided for illustrative purposes and thus they are not drawn to scale. Moreover, in the drawings like and / or corresponding elements are referred to by like reference numerals.
[0036]The present invention provides a bipolar transistor structure that includes a conductive back electrode for receiving a bias voltage, a second buried insulating layer located over the conductive back electrode, and a first semiconductor layer, which comprises an SOI layer of a SOI substrate, located over the second buried insulatin...
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