Switch level reliable transmission
a transmission level and switch technology, applied in the field of microprocessors, can solve the problems of increasing the overhead associated with current configuration, limiting the area available for main memory, and unused retry buffer space cannot be allocated for other memory purposes, so as to reduce overhead
Active Publication Date: 2007-04-03
ORACLE INT CORP
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AI Technical Summary
Benefits of technology
"The present invention provides a reliable transmission scheme that integrates retry buffers into main memory, reducing overhead. The invention can be implemented in various ways, such as a process, apparatus, system, device, or method. The invention allows for the selection and transmission of data packets between microprocessors, as well as the re-transmission of data packets if there are errors during transmission. The technical effects of the invention include improved data transmission reliability and efficiency."
Problems solved by technology
Providing this reliability tends to increase the overhead associated with the current configurations for reliably transmitting data between microchips.
As only a sub-set of the retry buffers may be used for storage of transmitted data, any unused retry buffer space can not be allocated for other memory purposes.
Moreover, the decode logic associated with the retry buffers further limits the area available for main memory.
Furthermore, the overhead associated with the retry buffers is excessive.
Method used
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[0020]An invention is described for a device and method for reliably transmitting data between microprocessors with minimal overhead. It will be obvious, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.
[0021]The embodiments of the present invention provide a device and method for the reliable transmission of data between microchips. A scheme for protecting the output from one memory to the input of another memory. The protection scheme employs two mechanisms. One of the mechanisms is a cyclic redundancy check and the other mechanism is a parity check. Both mechanisms protect the data transmission from soft errors. In addition, the retry buffers have been integrated into the memory, and replaced by retry pointers configured to point to an address in the memory. Acc...
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A microchip configured to reliably transmit data is provided. The microchip includes a memory region and a selection module configured to select a portion of the data from the memory region. An error checking module configured to calculate a value derived from the selected portion of the data is provided. A pointer region including a plurality of object pointers is included. One of the object pointers is associated with an address of the portion of the data. The object pointer associated with the address is configured to receive a signal indicating an error associated with the transmission of the data. A scheduler module in communication with each of the plurality of object pointers is provided. The scheduler module is configured to schedule re-transmission of the selected portion of the data. A system and a method for reliably transmitting data between microchips are also provided.
Description
BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates generally to microprocessors, and more specifically to a method and apparatus for the reliable transmission of data between microprocessors.[0003]2. Description of the Related Art[0004]In a multi-processor environment, it is important to transmit data between processors. Additionally, the transmission of data in the multi-processor environment requires the ability to re-transmit the data in the case of a detected error. Providing this reliability tends to increase the overhead associated with the current configurations for reliably transmitting data between microchips. In addition, the continuing quest to more efficiently use the chip real estate has demanded that an increasing amount of features be included on the die area in order to enable more functionality.[0005]FIG. 1 is a simplified schematic of two microprocessors in communication with each other over a high speed link. Chip 1100 is...
Claims
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IPC IPC(8): H04L1/18G06F15/163
CPCG06F11/1443G06F11/10G06F15/16
Inventor SHARMA, ANUP K.WONG, MICHAEL K.
Owner ORACLE INT CORP