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Semiconductor package

a technology of semiconductor devices and components, applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of insufficient heat radiation, difficult to radiate heat generated in the package,

Active Publication Date: 2010-01-12
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

Improves heat dissipation characteristics and reliability of the semiconductor package by efficiently transferring and radiating heat generated by multiple chips, even when the number of layers is increased.

Problems solved by technology

However, according to such a three-dimensional package structure, in which a plurality of semiconductor chips is layered in a vertical direction, it might become difficult to radiate heat generated in the package if the number of semiconductor chips in the package is increased.
However, according to the conventional technology shown in the above described publication, an sufficient extent of heat may not be radiated when the number of layers in a semiconductor package is increased.

Method used

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  • Semiconductor package
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first preferred embodiment

[0091]FIG. 1 is a plane view illustrating a semiconductor package according to a first preferred embodiment of the present invention; FIG. 2 is a cross-sectional view taken on line 2-2′ in FIG. 1; and FIG. 3 is an enlarged view illustrating a heat-radiation sheet.

[0092]A semiconductor package 001 according to the first preferred embodiment of the present invention, as shown in FIGS. 1-3, includes a substrate 101 having a first surface 111 and a second surface 112 opposing to the first surface 111; external connection terminals 201 formed on the second surface 112; first and second semiconductor chips 301a and 301b layered or laminated on the first surface of the substrate 101; and a heat-radiation sheet 400. The heat-radiation sheet 400 includes a first portion 401, arranged between the first semiconductor chip 301a and the second semiconductor chip 301b; and a second portion 402, extending at least from one side of the first portion 401 and connected to the substrate 101. Further, ...

second preferred embodiment

[0146]FIG. 7 is a plane view illustrating a semiconductor package according to a second preferred embodiment of the present invention; FIG. 8 is a cross-sectional view taken on line 8-8′ in FIG. 7; and FIG. 9 is an enlarged view illustrating a heat-radiation sheet.

[0147]A semiconductor package 001 according to the second preferred embodiment of the present invention, as shown in FIGS. 7-9, includes a substrate 101 having a first surface 111 and a second surface 112 opposing to the first surface 111; external connection terminals 201 formed on the second surface 112; first and second semiconductor chips 301a and 301b layered or laminated on the first surface of the substrate 101; and a heat-radiation sheet 400. The heat-radiation sheet 400 includes a first portion 401, arranged between the first semiconductor chip 301a and the second semiconductor chip 301b; and a second portion 402, extending at least from one side of the first portion 401 and connected to the substrate 101. Further...

third preferred embodiment

[0162]FIG. 11 is a plane view illustrating a semiconductor package according to a third preferred embodiment of the present invention; FIG. 12 is a cross-sectional view taken on line 11-11′ in FIG. 11; and FIG. 13 is an enlarged view illustrating a heat-radiation sheet 400.

[0163]A semiconductor package 001 according to the third preferred embodiment of the present invention, as shown in FIGS. 11-13, includes a substrate 101 having a first surface 111 and a second surface 112 opposing to the first surface 111; external connection terminals 201 formed on the second surface 112; first and second semiconductor chips 301a and 301b layered or laminated on the first surface of the substrate 101; and a heat-radiation sheet 400. The heat-radiation sheet 400 includes a first portion 401, arranged between the first semiconductor chip 301a and the second semiconductor chip 301b; and a second portion 402, extending at least from one side of the first portion 401 and connected to the substrate 10...

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Abstract

A semiconductor package according to the present invention includes a substrate; first and second semiconductor chips mounted on a first surface of the substrate; and a heat-radiation sheet. The heat-radiation sheet includes a heat-transferable conductive layer and first and second insulating layers formed on top and bottom surfaces of the heat-transferable conductive layer, respectively. The heat-radiation sheet includes a first portion arranged between the first semiconductor chip and the second semiconductor chip; and a second portion extending at least a side of the first portion. The second portion is connected to the substrate. The second insulating layer of the second portion is formed to expose a part of the heat-transferable conductive layer.

Description

CROSS REFERENCE TO RELATED APPLICATION[0001]This application claims the priority of Application No. 2005-287552, filed on Sep. 30, 2005 in Japan, the subject matter of which is incorporated herein by reference.TECHNICAL FIELD OF THE INVENTION[0002]The present invention relates to, a semiconductor package and a method for fabricating the same. Particularly, the present invention relates to a three-dimensional package for semiconductor devices and a method for fabricating the same.BACKGROUND OF THE INVENTION[0003]Conventionally, for minimizing a semiconductor package, a multi-chip package structure has been used, in which a plurality of semiconductor chips is mounted in a single package to improve the packaging density. One type of such a multi-chip package structure is a three-dimensional package, in which a plurality of semiconductor chips is layered in a vertical direction.[0004]However, according to such a three-dimensional package structure, in which a plurality of semiconductor ...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01L23/02
CPCH01L21/6835H01L23/552H01L24/81H01L24/86H01L24/97H01L25/0657H01L25/50H01L2221/68345H01L2223/6627H01L2224/13144H01L2224/13147H01L2224/81101H01L2224/81801H01L2224/97H01L2225/06517H01L2225/06541H01L2225/06572H01L2225/06579H01L2225/06589H01L2924/01013H01L2924/01029H01L2924/01078H01L2924/01079H01L2924/01082H01L2924/15311H01L2924/1903H01L2924/3025H01L2224/81H01L2924/01005H01L2924/01006H01L2924/01033H01L2924/014H01L2224/05573H01L2224/05624H01L2224/05647H01L2224/06135H01L2224/13025H01L2224/16227H01L2224/81191H01L2924/351H01L2924/00H01L2924/00014
Inventor EGAWA, YOSHIMI
Owner TAIWAN SEMICON MFG CO LTD