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Implementing APS voltage level activation with secondary chip in stacked-chip technology

a secondary chip and voltage level technology, applied in the field of data processing, can solve the problems of increasing the difficulty of designing and manufacturing sense amplifiers, affecting the design and manufacture of the amplifier, and affecting the operation of the power supply system

Inactive Publication Date: 2011-01-04
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This solution enhances power requirements and chip circuit yield by eliminating the need for blowing and sensing eFuses, ensuring secure and reliable system voltage level activation without the risks associated with eFuses, and reduces chip discarding due to higher pre-boot voltage requirements.

Problems solved by technology

However, reliability is a problem with using eFuses, for example, blowing of fuses can damage a portion of the chip.
Containing damage cannot always be guaranteed under all operating conditions.
Also it is a problem to reliably sense the state of the fuse or determine whether the fuse is blown or is it not.
This resistance change requires sensitive sense amplifiers that are becoming increasingly difficult to design and manufacture in shrinking technologies.

Method used

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  • Implementing APS voltage level activation with secondary chip in stacked-chip technology
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  • Implementing APS voltage level activation with secondary chip in stacked-chip technology

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Embodiment Construction

[0025]In accordance with features of the invention, using an Adaptive Power Supply (APS) in accordance with the preferred embodiment enables advantages in both power requirements and chip circuit yield. In the prior art APS systems, APS settings must first be read from respective eFuses before APS boot-up. In order to accomplish reading the APS settings from eFuses, a significant portion of the chip must boot-up with a common voltage. With APS settings connected directly to VDD or GND on a secondary chip in accordance with the preferred embodiment the boot process now ramps to VDD until the APS settings are recognized as ones and zeros. Once this has been accomplished the APS voltage is activated to the proper operating voltage.

[0026]Having reference now to the drawings, in FIG. 5, there is shown an adaptive power supply (APS) generally designated by the reference character 500 in accordance with the preferred embodiment. APS system 500 includes a secondary chip stacked chip circuit...

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PUM

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Abstract

A method and apparatus implement adaptive power supply (APS) system voltage level activation eliminating the use of electronic Fuses (eFuses), and a design structure on which the subject circuit resides are provided. A primary chip includes an adaptive power supply (APS). A secondary chip circuit includes at least one pair of hard-wired APS setting connections. Each hard-wired APS setting connection is defined by a selected one of a voltage supply connection and a ground potential connection. A respective inverter couples a control signal from each of the hard-wired APS setting connections to a power communication bus connected to the APS on the primary chip.

Description

[0001]This application is a continuation-in-part application of Ser. No. 11 / 739,723 filed on Apr. 25, 2007.FIELD OF THE INVENTION[0002]The present invention relates generally to the data processing field, and more particularly, relates to a method and apparatus for implementing adaptive power supply (APS) system voltage level activation eliminating the need for using electronic fuses (eFuses), and a design structure on which the subject circuit resides.DESCRIPTION OF THE RELATED ART[0003]Electronic fuses (eFuses) are one time electrically programmable elements that are written or blown with an external voltage that modifies the fuse resistance, allowing the fuse to retain its local state over time, powering on / off, and the like. Chip security is accomplished by blowing fuses at several stages of the product's design cycle including wafer test, module test, system test, lab use, customer use and returns.[0004]Electronic Fuses (eFuses) are currently used to configure elements after th...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G06F17/50
CPCG06F1/26
Inventor PAONE, PHIL C.PAULSEN, DAVID PAULSHEETS, II, JOHN EDWARDUHLMANN, GREGORY JOHN
Owner GLOBALFOUNDRIES INC