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Buffer chain management for alleviating routing congestion

a buffer chain and congestion technology, applied in the field of electronic design automation, can solve the problems of long time and poor quality, and achieve the effect of alleviating congestion caused by buffer chains

Active Publication Date: 2017-04-04
SYNOPSYS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This method effectively reduces routing congestion quickly and efficiently, even in large circuit designs, by redistributing buffer chains and optimizing their placement, thereby improving the quality of results and reducing computational time.

Problems solved by technology

Performing placement and routing on large circuit designs using conventional techniques and can take a long time and / or lead to poor quality results.

Method used

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  • Buffer chain management for alleviating routing congestion
  • Buffer chain management for alleviating routing congestion
  • Buffer chain management for alleviating routing congestion

Examples

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Embodiment Construction

[0019]The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Overview of an EDA Flow

[0020]An EDA flow can be used to create a circuit design. Once the circuit design is finalized, it can undergo fabrication, packaging, and assembly to produce integrated circuit chips. An EDA flow can include multiple steps, and each step can involve using one or more EDA software tools. Some EDA steps and software tools are described b...

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PUM

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Abstract

Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. Next, the set of the buffer chains can be removed from the circuit design. A placement blockage in the circuit design can then be created that covers at least a portion of the congested region. Next, the buffer chains that were removed can be reconstructed in the circuit design in the presence of the placement blockage, thereby alleviating congestion. Once the buffer chains have been reconstructed, the placement blockage can be removed from the circuit design. In some embodiments, congestion can be alleviated by spreading out buffer chains based on spreading out center of mass lines corresponding to the buffer chains.

Description

TECHNICAL FIELD[0001]This disclosure relates to electronic design automation (EDA). More specifically, this disclosure relates to buffer chain management for alleviating routing congestion.BACKGROUNDRelated Art[0002]Advances in process technology and an almost unlimited appetite for consumer electronics have fueled a rapid increase in the size and complexity of integrated circuit (IC) designs. The performance of EDA tools is very important because it reduces the time to market for IC designs.[0003]Placement and routing are two important processes that are performed in an EDA flow. Placement involves determining locations for circuit objects (e.g., cells instances, macros, etc.) in the circuit design. Routing involves determining routes for metal wires which electrically connect circuit objects to produce circuits that perform desired functions. Performing placement and routing on large circuit designs using conventional techniques and can take a long time and / or lead to poor quality...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G06F17/50
CPCG06F17/5081G06F30/392G06F30/394G06F30/398
Inventor TAI, PHILIP H.
Owner SYNOPSYS INC