Computer system controller having internal memory and external memory control

Abstract

The present invention relates generally to an optimized memory architecture for computer systems and, more particularly, to integrated circuits that implement a memory subsystem that is comprised of internal memory and control for external memory. The invention includes one or more shared high-bandwidth memory subsystems, each coupled over a plurality of buses to a display subsystem, a central processing unit (CPU) subsystem, input/output (I/O) buses and other controllers. Additional buffers and multiplexers are used for the subsystems to further optimize system performance.

Description

[0001]More than one reissue application has been filed for the reissue of U.S. Pat. No. 6,690,379. The reissue applications are application Ser. No. 11 / 351,220, filed Feb. 2, 2006 (the present application), and reissue application Ser. No. 12 / 562,983, filed Sep. 18, 2009, which is a continuation reissue of present reissue application Ser. No. 11 / 351,220.<?insert-end id="INS-S-00001" ?>RELATED APPLICATIONS[0002]This patent application is a continuation application of U.S. patent application Ser. No. 09 / 541,413, filed on Mar. 31, 2000 now abandoned entitled “Computer System Controller Having Internal Memory and External Memory Control,” naming Neal Margulis as inventor, which is a continuation application of U.S. patent application Ser. No. 08 / 926,666, filed on Sep. 9, 1997, now U.S. Pat. No. 6,118,462, which resulted from a continuation-in-part application of U.S. patent application Ser. No. 08 / 886,237, filed on Jul. 1, 1997, entitled “Computer System Having a Common Display Me...

AI Technical Summary

Benefits of technology

[0018]The present invention resides in a memory architecture having one or more high bandwidth memory subsystems where some of the memory subsystems are external to the controller and some of the memory subsystems are internal. Each of the high bandwidth memory subsystems is shared and connected over a plurality of buses to a display subsystem, a central processing unit (CPU) subsystem, input/output (I/O) buses and other controllers. A display subsystem is c

Problems solved by technology

However, the graphics display subsystem memory and the main system's pool of memory do not share data efficiently or move data efficiently from one memory subsystem to the other.

Even though these single external memory systems can support a cache memory for the CPU, their overall performance is still lower because the memory bandwidth is shared between the graphics and CPU subsystems.

These computer systems are very limited in their ability to achieve good performance for both the CPU and graphics subsystems.

For systems that use a single external memory subsystem to perform all of their display refresh and drawing operations, performance is compromised by the memory bandwidth for these operations being shared with the memory bandwidth for the CPU.

For high-resolution color systems, the refresh process consu

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