9 results about "Record entry" patented technology

A graphics processor that is operable to perform ray tracing. Determining if a ray tracing circuit of the GPU may require additional storage space to store test record entries to trace a ray, allocati

The invention relates to the technical field of data processing, can be applied to business system platforms of financial science and technology, medical health and the like, and discloses a data migration method, which comprises the following steps of: dividing a to-be-migrated data set in a source database into a preset number of data batches, and writing a batch label of each data batch into a preset task list file; and creating a corresponding record entry for each batch label in a preset progress record file, generating a loading task for each data batch according to the division sequence, sending the loading task to the target database, monitoring the loading state, and marking the state and timestamp of each stage in the progress record file. According to the method, the breakpoint is accurately identified by utilizing the task list file and the progress record file, the recovery mode is automatically entered, and automatic and intelligent data migration is realized.

The application discloses a switch configuration method and device based on an SDN network and a medium, belongs to the field of communication technology, and is used for solving the technical problems of the recovery configuration of the existing network device, the matching error of the configuration command, the long configuration time and the difficulty in checking and comparing the configuration of the switch. The method comprises the following steps: based on a preset time interval, the configuration information of the switch is stored correspondingly; through an SDN controller, the first record entry of the switch to be recovered is acquired, and the first configuration information is obtained according to the first record entry; the second configuration information corresponding to the second record entry is acquired, and the first configuration information is compared with the second configuration information to obtain the effective configuration information; wherein the second record entry corresponds to the switch to be recovered; and the effective configuration information is transmitted to the switch to be recovered to complete the configuration recovery of the switch to be recovered.

The invention relates to a live broadcast microphone connection interaction method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: displaying a live broadcast page of a target live broadcast, wherein the live broadcast page comprises a microphone connection entrance; in response to a trigger operation for the microphone connection entry, displaying a content recording page, the content recording page comprising a recording entry; and in response to completion of recording of the target content based on the recording entrance, sending a microphone connection request to an anchor account of the target live broadcast, the microphone connection request comprising the target content. By adopting the method, the overall quality and efficiency of microphone connection interaction can be remarkably improved.

Various implementations of a system and method may include a secure database that can be structured with a strong emphasis on individual entity permissions and enforcement of read, write, and audit policies relative to individual database record entries to close security and privacy gaps that exist in current database systems.

A method for combining multiple interactions into a single record entry is disclosed. A data package can be created that represents a set of interactions, and each entity associated with an interaction can review the data package. Each entity can indicate agreement with the interactions by digitally signing the data package. Once signed by each involved entity, the data package can be stored in a record such as a blockchain.

This invention relates to the field of address translation cache invalidation technology, and in particular to a method and system for global invalidation of address translation cache based on generational flags. This invention maintains a current generational flag for each function identifier and records an entry generational flag for each address mapping entry. When a global invalidation request is received, only the current generational flag of the target function identifier is flipped, without traversing any address mapping entries. During a query, the entry generational flag is compared with the current generational flag of the function identifier: if they are not equal, the entry is marked as invalid and a re-request is triggered. Thus, global invalidation is reduced from traversing N entries to flipping only one flag bit, the time complexity is reduced from O(N) to O(1), eliminating performance jitter; the storage overhead is only a few KB, and the hardware implementation is simple; the comparison operation can be performed in parallel with the query step without increasing latency.

The application provides a processor scoreboard under a VLIW architecture, a processor and an electronic device, after entering a current clock cycle, the first scoreboard is used for writing the hazard information sent by an n-th decoding slot received in a previous clock cycle into an n-th record entry in a target table item, and marking the n-th record entry as an effective state; after entering the current clock cycle, the first scoreboard is also used for moving the record entry in a k-th table item in the effective state to a corresponding record entry in a k-1-th table item, and marking the corresponding record entry as the effective state. The number of table items is used to dynamically represent the number of execution cycles of the pipelined instruction in the execution unit, the execution state of the instruction is efficiently tracked and the write-back information is dynamically updated, the hardware logic is significantly simplified, the execution management of the indefinite cycle instruction and the pipelined instruction is supported, and the hardware efficiency and the instruction execution throughput are improved.