System and method for a fully synthesizable superpipelined VLIW processor

Abstract

The invention relates to a method to create a fully synthesizable super-pipelined VLIW processor that creates both a high frequency operating processor as well as a high performance processor. It is proposed to split the operation units of the VLIW into two subsets. The first subset unit executes a basic loop with only a single register delay in the loop as the other unit, although connected around the first unit, has the conventional delay in the loop.

Description

technical field [0001] The present invention relates to a method for creating a fully synthesizable super-pipelined VLIW (Very Long Instruction Word) processor, which results in a high frequency working processor and a high performance processor. Background technique [0002] The VLIW central processing unit (CPU) is a well-known CPU architecture that has very good performance per silicon area compared to other CPU architectures, especially for signal processing and other parallelizable computations This is especially the case. To illustrate the VLIWCPU design, please refer to Computer Architecture: A Quantitative Approach', John L. Hennessy , David A. Patterson , David Goldberg , Morgan Kaufmann Publishers; ISBN: 1558605967; 3 rd edition (May 15, 2002). [0003] In the case of the same process and the same design style, the clock speed of VLIW CPU is usually close to but slightly lower than that of RISC processor. For example, fully synthesizable ARM and MIPS RISC ...

AI Technical Summary

Problems solved by technology

Problem 3, i.e. VLIW CPU bypass loop is a major problem

If the bypass loop itself is also superpipelined, for example by inserting an extra pipeline stage into it, then the VLIW CPU will effectively run at 1.8x the clock speed immediately, but double the critical path for each computation in clock cycles, Because all actions will now take twice as many clocks, resulting in no actual speedup

Note: a slight speedup is possible because more operations can be performed per time unit; but for programs bounded by the critical path of computation, i.e., there is no shortage of functional units in the original VLIW CPU, Then you can't get the overall speed advantage

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