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Method for making MOS transistor with source-drain on insulating layer

A technology of a MOS transistor and a manufacturing method, which is applied to the manufacturing field of MOSFET transistors, can solve the problems of large source-drain parasitic capacitance and leakage, and the threshold voltage swing is difficult to eliminate, and achieves small source-drain parasitic resistance, high practical value, and improved performance. Effect

Inactive Publication Date: 2007-12-19
PEKING UNIV +1
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  • Summary
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  • Claims
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Problems solved by technology

However, Superhalo doping requires a very precise doping distribution, which is difficult to achieve in the actual process; secondly, traditional bulk silicon MOSFET devices using Superhalo doping technology have large source-drain parasitic capacitance and leakage; Thirdly, since the channel is relatively highly doped, the threshold voltage swing caused by impurity fluctuations is also difficult to eliminate in Super halo doped MOSFET devices

Method used

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  • Method for making MOS transistor with source-drain on insulating layer
  • Method for making MOS transistor with source-drain on insulating layer
  • Method for making MOS transistor with source-drain on insulating layer

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Embodiment Construction

[0052] A specific embodiment of the manufacturing method of the present invention comprises the process steps shown in Fig. 1 to Fig. 9:

[0053] The crystal orientation of the single crystal silicon substrate used is (100), the body region is initially lightly doped, B + Ion implantation, the implantation dose is 1e+16 / cm -2 , the implantation energy is 20KeV, and a highly doped silicon region is obtained on the surface, as shown in FIG. 1 .

[0054]An undoped silicon film is epitaxially grown on highly doped silicon with a thickness of 5-30 nm, as shown in FIG. 2 .

[0055] The active region isolation layer is fabricated by conventional CMOS shallow trench isolation technology, as shown in FIG. 3 .

[0056] Then a gate dielectric layer is grown, the gate dielectric layer is silicon dioxide, and its thickness is 1-1.5nm. The gate dielectric can also be formed by one of the following methods: conventional thermal oxidation, nitrogen-doped thermal oxidation, chemical vapor d...

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Abstract

The invention discloses a method for preparing MOSFET transistor that have drain and source on insulating layer which includes: exploiting diffusing or ions injecting and extension techniques, forming low doped layer on semiconductor base surface and also forming a high doped buried layer under it; afterwards, etching the high doped layer under the source and drain with selective etching technique, filling the holes left after etching with materials to form insulating layer under source and drain. The inventive method is compatible with conventional CMOS process and has high practicability.

Description

Technical field: [0001] The invention belongs to the technical field of semiconductor integrated circuits and its manufacture, and in particular relates to a method for manufacturing a MOSFET transistor whose source and drain are located on an insulating layer. Background technique: [0002] The main device in an integrated circuit, especially a VLSI, is a metal oxide semiconductor field effect transistor (MOSFET for short). The continuous reduction of device size can improve the performance of MOSFET devices, and can greatly increase the integration density of a single chip. And with the continuous expansion of chip size, circuit functions are also increasing. Now, the geometric dimensions of MOSFETs have entered the nanometer scale. [0003] When the geometric size of MOSFET devices enters the nanometer scale, various microscopic effects appear one after another, seriously affecting the further improvement of device performance with size reduction. In order to continuou...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336
Inventor 张盛东李定宇柯伟孙雷韩汝琦
Owner PEKING UNIV
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