Multilayer mos device and preparation method thereof

Abstract

The invention provides a multi-layer MOS device and a preparation method thereof. The preparation method includes the following steps: S1, providing an n-layer MOS device, where n is a natural number greater than 0, forming a semiconductor layer on the n-layer MOS device, and sequentially forming a gate oxide layer and a dummy gate on the semiconductor layer, at least part of the gate oxide layer The layer is located between the dummy gate and the semiconductor layer; S2, a metal silicide layer is formed in the semiconductor layer on both sides of the corresponding dummy gate, and the metal silicide layer is used as a metallized source and drain region or the metal silicide layer is doped to form a metal silicide layer. The source and drain regions are formed to obtain the n+1th layer MOS device; S3, the nth layer MOS device and the n+1th layer MOS device are metal interconnected. The above preparation method reduces the requirement of the conventional process for doping activation temperature, reduces the adverse effects of parasitics and contact resistance increase on the device caused by insufficient activation of impurities, improves the process defects of the existing single-chip three-dimensional integration, and improves the performance of the device. performance of multilayer MOS devices.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, and in particular, to a multi-layer MOS device and a preparation method thereof. Background technique [0002] The miniaturization of CMOS integrated circuits continues to develop, with devices ranging from 2D planar structures to 3D FinFETs, to 3D LateralGAA NW FETs and 3D Vertical GAA NW FETs, and will develop to vertical single-chip three-dimensional integration (M3D) in the future. [0003] Microsystem integration based on CMOS integrated circuits has also developed from three-dimensional packaging, system-in-package (SiP), multi-chip three-dimensional system integration (3D-SoC) to single-chip three-dimensional integration (3D-IC) to continuously reduce the size of microsystems, Reduce circuit delay and power consumption, greatly improve system performance. [0004] Multi-layer MOS devices can be formed through the above single-chip three-dimensional integration process. For ...

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Problems solved by technology

[0005] The main purpose of the present invention is to provide a multilayer MOS device and its preparation method to solve the problem of poor performance of multilayer MOS devices in the prior art

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