A MOS resistor and its manufacture method

A technology of MOS transistors and manufacturing methods, which is applied in the field of MOS transistors with new structures and their manufacturing, can solve the problems of reducing the on-state current of devices, high thermal budget, and difficulty in application, and achieve the reduction of off-state leakage current and switch-state current The effect of improving and lowering the thermal budget

Inactive Publication Date: 2008-12-31
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Some researchers have proposed a Schottky barrier source-drain MOSFET with source-drain elevation, that is, a recessed gate. This structure device has a large on-off current ratio, but its source terminal is raised while reducing the device On-state current, and at the same time, there are difficulties in the realization of the device process at the nanometer scale
Some researchers have also proposed that the source end uses metal or metal silicide to form a Schottky barrier, and the drain end uses doping implantation to form a PN junction. This device structure has good device characteristics, but self-alignment cannot be achieved in the process. Simultaneous doping Implantation is done after the gate structure is formed, which means a high thermal budget, making it difficult to apply to nanoscale MOSFET fabrication

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  • A MOS resistor and its manufacture method
  • A MOS resistor and its manufacture method
  • A MOS resistor and its manufacture method

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Embodiment Construction

[0039] The following specific embodiments are helpful to understand the features and advantages of the present invention, but the implementation of the present invention is by no means limited to the described embodiments.

[0040] A specific embodiment of the manufacturing method of the present invention includes Figure 1 to Figure 6 Process steps shown:

[0041] 1. Such as figure 1 As shown, the crystal orientation of the bulk silicon wafer silicon substrate (1) used is (100), the body area is initially lightly doped, and the active area isolation layer is made on the substrate using conventional CMOS shallow trench isolation technology; and then proceed Ion implantation, the energy of the ion implantation is 30KeV, and the implanted impurity is As; then a layer of TEOS dielectric protective layer (2) is deposited with a thickness of 50-100nm.

[0042] 2. Such as figure 2 As shown, photolithography is performed once to etch the TEOS dielectric protective layer (3), and then the...

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Abstract

The provided MOS transistor comprises asymmetric source and drain structures. Wherein, the source uses metal or metal-semiconductor compound and channel to form Schottky barrier contact, while the drain is boost high doped. Compared with traditional MOSFET device, this invention increases on-off current rate greatly, compatible to traditional manufacture technology, and has much room for high-K grid medium and metal grid material since low thermal budget.

Description

Technical field: [0001] The invention belongs to the technical field of semiconductor integrated circuits and their manufacturing, and particularly relates to a MOS transistor with a new structure and a manufacturing method thereof. Background technique: [0002] In the contemporary information society, under the dual drive of maximizing chip integration density and optimizing circuit performance, the core MOSFET devices of integrated circuits are continuously scaled down. With the continuous shrinking of MOSFET device size, when the feature size of the device enters the nanometer scale, integrated circuits with MOSFET as the core in many fields such as materials, structure and process have encountered more and more challenges. In order to meet these challenges, many new device structures and manufacturing methods have been proposed to be applied to the design and manufacture of nano-scale MOSFETs. [0003] Schottky barrier source-drain MOSFET is one of them. This structure devic...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L21/336
Inventor 孙雷李定宇张盛东吴涛韩汝琦刘晓彦
Owner PEKING UNIV
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