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Multi-clock domain system reset circuit

A multi-clock domain, system reset technology, applied in the direction of data reset device, generation/distribution of signals, etc., to achieve the effect of eliminating data transmission disorder

Inactive Publication Date: 2008-06-04
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0037] The technical problem to be solved by the present invention is the unexpected reset of the system when the reset signal in the prior art glitches, the timing degradation of the data path when the reset signal exists in the data path, the uncertain value of the flip-flop existing in the initial stage of simulation, and the failure of the reset signal time uncontrollable, data transmission error when the clock domain system is reset, etc., in order to propose a multi-clock domain system reset circuit that can overcome the shortcomings of the prior art

Method used

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Embodiment Construction

[0064] The reset circuit is divided into 3 parts:

[0065] 1. Reset signal deburring part;

[0066] 2. Asynchronous reset synchronization part;

[0067] 3. Reset signal sequence part.

[0068] The present invention will be described in further detail below in conjunction with the accompanying drawings.

[0069] Figure 4 Reset circuit for single clock domain system.

[0070] Figure 4 The device in the circuit contains a certain number of buffers (buffer 1, buffer 2, ..., buffer N), and the number of buffers is determined according to the glitch width of the external reset signal in the actual application and the transmission speed of the buffer used in the ASIC ), AND gate 1 of dual-input and single-output type, flip-flop 1 of asynchronous reset type, and flip-flop 2 of asynchronous reset type.

[0071] All the buffers (buffer 1, buffer 2, ..., buffer N) are arranged serially according to the serial number, and the output of the buffer with a lower serial number is conn...

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Abstract

This invention discloses one multi-clock zone system reset circuit, which comprises the following parts: signal lag parts; double input and single output gate one; asynchronous reset type main controller clock trigger one and two; asynchronous reset type pair control clock trigger one and two; asynchronous reset type controlled time trigger one and two. The invention circuit is not sensitive to the reset signal fuzzy without stable and normal situation.

Description

technical field [0001] The invention relates to the field of ASIC circuits, in particular to a realization circuit of a clock domain system reset circuit. Background technique [0002] In ASIC circuit design, the reset circuit mode is divided into synchronous reset ( figure 1 ) and asynchronous reset ( figure 2 ) two kinds. [0003] figure 1 It is a typical synchronous reset circuit. The reset signal of the synchronous reset circuit is ANDed with the data input and acts on the data input end of the flip-flop. The reset condition of the circuit is that the reset signal is valid at the effective edge of the clock. [0004] figure 2 It is a typical asynchronous reset circuit. The reset signal of the asynchronous reset circuit acts on the asynchronous reset terminal of the flip-flop. The reset condition of the circuit is that the reset signal is valid. [0005] Both types of reset circuits have advantages and disadvantages. [0006] The synchronous reset circuit has ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/24G06F1/04
Inventor 林晓涛陈家锦汪坚
Owner ZTE CORP