Bus controller and data buffer space allocation method

Abstract

The method is applicable to controlling a bus. The bus is in use for signal connections among multiple master control sets. The controller includes a data buffer unit and a logic circuit for controlling data buffer. The method includes steps: detecting number of bus master control set connected to bus; if the said number is larger than a default value, the said logic circuit makes the bus controller enter into first state of allocation; otherwise, if the said number is not larger than a default value, the said logic circuit makes the bus controller enter into second state of allocation. Quantity of data buffer space allocated for each master control set in second state is larger than quantity of data buffer space allocated for each master control set in first state.

Description

technical field [0001] The invention relates to a bus controller and a data buffer space allocation method, in particular to a bus controller and a data buffer space allocation method applied to a bus. Background technique [0002] Please refer to FIG. 1 , which is a schematic diagram of a functional block connection of a peripheral component interconnect bus (PCI Bus), in which a main control device 10 and a target device 11 are connected between the peripheral component interconnect bus 1 On the other hand, the main control device 10 can send a data read request to the target device 11 through the peripheral component connection interface bus 1, in order to make the target device 11 prepare the corresponding data, and then send the corresponding data through the peripheral component connection interface bus 1. The corresponding data is sent back to the main control device 10 for reception. However, in the traditional data read request specification, the total length of th...

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Problems solved by technology

However, when there are only two or one master devices connected to the peripheral component connection interface bus 1, each master device is still only fixedly assigned to 2 baskets, and when one master device stops due to insufficient buffer space When the bus is occupied, the probability that the only remaining master control device (even without another bus component device) is waiting in line to use the bus is of course smaller than the above-mentioned situation where multiple master control devices grab the bus, and the common methods are here Sometimes, the bus can only be placed in the idle state without knowing how to adapt it, so that the utilization rate of the bus will be greatly reduced, which will seriously affect the performance of the overall system.

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