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SIMD type parallel operation apparatus used for parallel operation of image signal

A technology for operating equipment and data, applied in the fields of electrical digital data processing, program control design, digital computer components, etc., and can solve problems such as complex programs

Inactive Publication Date: 2008-06-25
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when such determination is made in the operating device, the program established in the operating device becomes complicated

Method used

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  • SIMD type parallel operation apparatus used for parallel operation of image signal
  • SIMD type parallel operation apparatus used for parallel operation of image signal
  • SIMD type parallel operation apparatus used for parallel operation of image signal

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0082] FIG. 1 illustrates the structure of a SIMD type parallel operation device according to Embodiment 1 of the present invention. Reference numeral 1 denotes a processor unit group utilizing a plurality of processor units 5 as an operation unit of SIMD type. The processor unit group 1 outputs a read request as a memory control signal 2 , whereby the data at the position indicated by the post-conversion address 3 at this time is read out from the data memory 4 . The processor unit group 1 also performs processing of outputting a write request as a memory control signal 2 , thereby writing the result at the position indicated by the converted address 3 at this time. In the SIMD type processor unit group 1, the respective processor units 5 simultaneously execute the same processing. More specifically, each processor unit 5 is constituted in such a manner that pixel values ​​of an image signal of a horizontal period (equivalent to one line) are fetched to a memory circuit, the...

Embodiment 2

[0096] The structure of the SIMD type parallel operation device according to Embodiment 2 of the present invention is the same as that shown in FIG. 1 according to Embodiment 1 except for the structure of address conversion unit 7 . FIG. 5 illustrates the structure of the address conversion unit 7 according to Embodiment 2. As shown in FIG. Image 6 The operation of the address conversion unit 7 is shown.

[0097] Figure 7 A case is shown in which an image consisting of 8 horizontal pixels×8 vertical pixels and having 16 bits per pixel is set in the data memory 4 in a field format.

[0098] In the above case, it is assumed that sequential addresses are supplied to the address conversion register 6 and then Image 6 For the conversion operation shown in, control signal 9 is set to "1". With this operation, the sequential addresses are converted to the effective address sequence, and the read is performed using the converted address 3. Therefore, the image can be obtained i...

Embodiment 3

[0103] The structure of the SIMD type parallel operation device according to Embodiment 3 of the present invention is the same as that shown in FIG. 1 according to Embodiment 1 except for the structure of address conversion unit 7 . FIG. 8 illustrates the structure of the address conversion unit 7 according to Embodiment 3. As shown in FIG. Figure 9 The operation of the address conversion unit 7 is shown.

[0104] Figure 10 A case is shown in which an image consisting of 16 horizontal pixels×16 vertical pixels and having 16 bits per pixel is set in the data memory 4 in a frame format. Since one row of the image cannot be arranged in one row of the memory, the remainder of the image of the row is arranged in the next row of the memory. Fig. 11 shows the relationship between images and the arrangement of images in memory.

[0105] In the above case, it is assumed that sequential addresses are supplied to the address translation register 6 and then Figure 9 For the convers...

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Abstract

A parallel operation apparatus of a SIMD type comprises a processor element group of the SIMD type including a plurality of processor elements, wherein the respective processor elements simultaneously execute an identical operation, a data memory accessible from the respective processor elements in the processor element group, and an address conversion unit for converting an address with respect to the data memory accessed by the processor elements in accordance with a control signal by changing bit positions of the address. The address conversion unit preferably rearranges a first bit, a second bit, and a third bit from a lower order of address data into the second bit, the third bit, and the first bit from the lower order in the change of the bit positions.

Description

technical field [0001] The present invention relates to a single instruction multiple data (SIMD) type parallel operation apparatus for performing parallel operations on image signals such as image codecs (CODECs) and the like. Background technique [0002] In recent years, with the rapid development of technology in the field of digital image equipment, image processing such as image-related compression / expansion and filtering has become very complicated. In image processing, the images stored in the memory in the frame format or the field format are processed in the frame format or the field format, respectively. The frame format refers to a format in which top and bottom fields alternately constitute an image. The field format refers to a format in which the top field and the bottom field are respectively set at different positions, and each of the top field and the bottom field is regarded as a block. [0003] Fig. 33A shows a frame format consisting of eight horizonta...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06T1/20G06F15/80G06F12/02G06F12/00G06F15/00
CPCG06F9/345G06T1/20G06F9/3887G06F9/30181G06F9/3885
Inventor 寺田健吾田中健西田英志
Owner PANASONIC CORP
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