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Method and apparatus for setting and compensating read latency in a high speed DRAM

A technology of equipment and time, applied in information storage, static memory, digital memory information, etc., can solve the problems of uncertain data availability, difficult and difficult reading waiting time, etc.

Inactive Publication Date: 2008-12-24
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This will be difficult when the first and second clock domains are kept crossing each other
[0005] Since the amount of read clock back-off timing becomes indeterminate relative to data availability, it is very difficult to control the read clock and guarantee correct data output and specific read latencies as measured in external clock cycles

Method used

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  • Method and apparatus for setting and compensating read latency in a high speed DRAM
  • Method and apparatus for setting and compensating read latency in a high speed DRAM
  • Method and apparatus for setting and compensating read latency in a high speed DRAM

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Embodiment Construction

[0016] The present invention compensates for the uncertainty and variation of the read clock back timing in DRAM by transferring data to the output latch of the read clock from the correct timing to the back timing, so as to ensure that the correct read clock will be read with a specific read wait time. Data is transferred to the data bus.

[0017] FIG. 1 illustrates operative parts of a first embodiment of the invention as part of a memory device 100 . An external memory controller 160 provides an external system clock XWCLK to memory device 100 on external clock line 116 and command and address signals on command / address bus 112 . Memory array data is exchanged between controller 160 and memory device 100 on a multi-bit data bus represented in FIG. 1 by a data line 108 of the bus. Since the present invention is specifically directed to the timing of read operations that occur within the memory device 100, data lines 108 are shown passing selected read data from a memory arr...

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Abstract

An apparatus and method for coordinating the variable timing of internal clock signals derived from an external clock signal to ensure that read data and a read clock used to latch the read data arrive at the data latch in synchronism and with a specified read latency. A read clock is produced from the external clock signal in a delay lock loop circuit and a start signal, produced in response to a read command, is passed through a delay circuit slaved with the delay lock loop so that the read clock signal and a delayed start signal are subject to the same internal timing variations. The delayed start signal is used to thereby control the output of read data by the read clock signal.

Description

field of invention [0001] The present invention relates to a DRAM circuit, and more particularly to a circuit and method for ensuring correct data output from a high speed DRAM with correct read latency. Background of the invention [0002] A typical DRAM memory system has an external DRAM controller that generates read and write requests to the DRAM memory device. When a read request is generated, the controller expects to obtain data within the memory device on a data bus with a predetermined read latency after the controller generates a read request, which is usually a predetermined number of external system clock cycles, for example eight external clock cycles. Internally, the DRAM memory device has its own clock system that receives an external clock signal and generates from this external clock several different internal clock signals for the internal operation of the memory device. [0003] A known internal clock system of a high speed memory device generates at lea...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C7/10G11C11/4076
CPCG11C7/1051G11C7/106G11C7/1066G11C11/4076G11C2207/2281G11C7/222G11C11/4096G11C2207/2272
Inventor B·凯思B·约翰逊F·林
Owner MICRON TECH INC