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Making contact with the emitter contact of a semiconductor

A semiconductor and conductor technology, applied in the field of manufacturing semiconductor devices, can solve problems such as limitations, small utilization, and the need for high emitter collection current intensity

Inactive Publication Date: 2009-01-07
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The engineering demands of this procedure may result in more noticeable yield losses
[0014] In addition to process engineering difficulties limited by the above-mentioned conventional semiconductor device production (necessary program window for CMPBPSG and CT etching process steps), in known semiconductor devices of this type, the contact surface area of ​​the emitter contact 14 is disadvantageously limited by the surface area of ​​the contact hole 32
Bipolar applications, which require high emitter collection current densities, can only be realized to a limited extent due to the smaller than optimal utilization of the cross-section of the emitter contact point 14

Method used

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  • Making contact with the emitter contact of a semiconductor
  • Making contact with the emitter contact of a semiconductor
  • Making contact with the emitter contact of a semiconductor

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Embodiment Construction

[0084] figure 1 A cross-sectional view is shown of a preferred embodiment of a semiconductor device according to the first aspect of the present invention. The semiconductor device is in a process stage where active components such as bipolar transistor 10 and MOS transistor 20 have been completed. The end of the FEOL (Before End of Line) procedure, where especially high temperature steps may occur, has thus been achieved.

[0085] Such as figure 1 As shown, in a subsequent process step, the entire semiconductor device is covered with a dielectric insulating layer 30, which may, for example, be BPSG (borophosphosilicate glass), preferably by a CVD deposition step (CVD BPSG step). The insulating layer 30 is typically applied in a layer height approaching 1400 nm. This layer coverage is significantly greater than the height of the emitter contact 14, which is typically 550 nm, and greater than the height of the gate contact 24, which is typically 280 nm.

[0086] Subseque...

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Abstract

The invention relates to a semiconductor device having a substrate (8) whose processing surface (8') has a normal direction of the substrate; at least one first contact point (12, 16, 22, 24, 26) and a second contact The point (14) is arranged on the base plate, and a contact point surface of the second contact point (14) is farther from the base plate (8) than a contact point surface of the first contact point (12, 16, 22, 24, 26). The substrate has a larger distance in the normal direction; and at least a first (34) and a second (40) patterned metal plane, at least one conductor in each of them, which can be connected to at least one contact point. is formed; the second metal plane (40) is farther away from the substrate (8) than the first metal plane (34) in the normal direction of the substrate, and the second contact point (14) is electrically connected to the A conductor of the second metal plane (40) normal to the substrate without a conductor of the first metal plane (34) is connected therebetween, and the first contact points (12, 16, 22, 24, 26) are Electrically connected to a conductor located on the first metal plane (34) normal to the substrate.

Description

technical field [0001] The present invention relates to semiconductor devices and to methods for manufacturing semiconductor devices. Background technique [0002] Figure 16 A conventional semiconductor device is shown which will be used to demonstrate the problems of the prior art with which the present invention is affected. The semiconductor device comprises a (vertical) bipolar transistor 10 which, in a known manner, has a base contact 12 , an emitter contact 14 and a collector contact 16 . The bipolar transistor 10 may be an npn transistor or a pnp transistor, which forms, for example, part of a radio frequency circuit of a semiconductor device. Furthermore, a CMOS circuit, comprising in the simplest example a MOS transistor 20 with a source contact 22, a gate contact 24 and a drain contact 26, may be provided on the same substrate 8 ( such as a silicon wafer). [0003] A characteristic pattern of bipolar CMOS circuits of this type is that the emitter contact (as kn...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/528H01L21/768H01L29/417H01L21/8249H01L23/485H01L27/06
CPCH01L23/5283H01L23/485H01L21/76838H01L29/41708H01L21/8249H01L27/0623H01L2924/0002H01L2924/00
Inventor K·戈尔勒
Owner INFINEON TECH AG