Method for forming gate dielectric layers

Abstract

A method for forming gate dielectric layers having different thicknesses is provided. The method includes forming a lower oxide layer, a nitride layer, and an upper oxide layer on a semiconductor substrate; performing a first deglaze process to the semiconductor substrate keeping the lower oxide layer, the nitride layer, and the upper oxide layer in a first region, while removing the nitride layer and the upper oxide layer in second, third, and fourth regions; forming the first gate dielectric layer having a first thickness in the second, third, and fourth regions; performing a second deglaze process to the first gate dielectric layer in the third region, thereby forming a second gate dielectric layer having a second thickness; and performing a third deglaze process on the first gate dielectric layer on the fourth region, thereby forming a third gate dielectric layer having a third thickness. The method is used for forming gate dielectric layers with different thickness.

Description

technical field [0001] The invention relates to a semiconductor device, in particular to a method for forming gate dielectric layers with different thicknesses, which can improve the hump characteristics of logic devices in embedded devices. Background technique [0002] Embedded devices including silicon-oxide-nitride-oxide-silicon (SONOS) devices have various transistors as main constituent elements. Such constituent transistors require gate dielectric layers of varying thickness. For this purpose, a gate dielectric layer having an appropriate thickness is formed by performing an oxidation process twice or three times, and a deglaze process is repeatedly performed to selectively remove a part of the oxide layer. [0003] However, the cleaning process performed repeatedly may cause severe defects in the edges of STI (Shallow Trench Isolation) films of some devices such as low-voltage logic transistor devices. This is the so-called hump phenomenon. This humping causes cur...

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Problems solved by technology

Subsequently, if figure 2 As shown, by performing some processing (for example, by repeatedly performing cleaning processing) to control the thickness of the gate dielectric layer 20, the edge 30 of the shallow trench isolation film 15 is chipped, thereby causing a hump phenomenon.

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