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Circuit for class D amplifier

A class D amplifier and circuit technology, applied in the direction of amplifiers, amplifiers with semiconductor devices/discharge tubes, electrical components, etc., can solve the problems of inability to meet the standard of undistorted human hearing and increased distortion rate

Active Publication Date: 2009-04-08
MEDIATEK INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as mentioned earlier, the current process capability only provides a minimum pulse width of about 50 nanoseconds, which obviously cannot meet the undistorted standard for human hearing.
In a general Class D amplifier, the uncorrected large signal distortion is between -35dB and -45dB, but the distortion rate also increases rapidly as the signal level decreases

Method used

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  • Circuit for class D amplifier
  • Circuit for class D amplifier

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0024] Please refer to figure 1 , which is a schematic diagram of the class D amplifier circuit 100 according to the first embodiment of the present invention. The class D amplifier circuit 100 includes a class D amplifier 110 and a modulation circuit 120 coupled to each other. The first control circuit 112 of the class D amplifier 110 is used to provide the first pulse width modulation (Pulse WidthModulation, PWM) signal to the four switch elements of the class D amplifier 110, namely four transistors MP1, MP2, MN1, MN2, to control The switching action of these switching elements. In this embodiment, both the transistors MP1 and MP2 are PMOS, and the transistors MN1 and MN2 are both NMOS. The class D amplifier 110 further includes a load 115 such as an inductor.

[0025] like figure 1 As shown, the sources of the transistors MP1 and MP2 are coupled to a first voltage level Vcc, the drains are coupled to the load 115 , and the gates are coupled to the first control circuit...

no. 2 example

[0029] Please refer to figure 2 , which is a schematic diagram of a class D amplifier circuit 200 according to the second embodiment of the present invention. The difference from the first embodiment is that the modulation circuit 130 of the class D amplifier circuit 200 uses two PMOS transistors MP3 and MP4 as switching elements. In addition, if figure 2 As shown, the sources of the transistors MP3 and MP4 are coupled to the first voltage level Vcc instead of the second voltage level, the drains are coupled to the load 115 , and the gates are coupled to the second control circuit 132 . Utilizing the function of the modulating circuit 130, the class D amplifier circuit 200 can also improve existing problems, and apply designs such as negative feedback.

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PUM

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Abstract

A class-D switching amplifier is disclosed. The class-D switching amplifier includes two control circuits, a load, and six switching devices. The load is coupled to the six switching devices. The first and the second control circuits provide a first and a second PWM pulse respectively. Each of the first and second switching devices has a first terminal coupled to a first voltage level, a second terminal coupled to the load, and a control terminal coupled to the first control circuit. Each of the third, fourth, fifth, and sixth switching devices has a first terminal coupled to a second voltage level, and a second terminal coupled to the load. The control terminals of the third and fourth switching devices are coupled to the first control circuit. The control terminals of the fifth and sixth switching devices are coupled to the second control circuit.

Description

technical field [0001] The invention relates to a class D amplifier circuit, in particular to a class D amplifier circuit whose internal circuit can modulate circulating current to reduce signal distortion. Background technique [0002] The carrier frequency of the class D amplifier, that is, the duty cycle of the PWM signal generator, is generally between 200 kHz and 2 MHz. At the highest output power, the signal is high for the entire cycle; at 50% of the maximum output power, the signal is high for half a cycle, and the level decreases linearly with the desired audio level. Since the output power is proportional to the output pulse width, the degree of signal distortion is also proportional to the error, which is the error between the effective pulse width and the required pulse width. In the case of a large signal, although the error is small, in the case of a small input signal, the error is large. For the traditional CMOS technology used in class D amplifiers, the mi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03F3/217
Inventor 泰利·罗伯特
Owner MEDIATEK INC
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