Design and implementing method of multimedia expansion instructionof flow input read
A technology for extending instructions and implementing methods, applied in computing, image data processing, television and other directions, can solve the problem of not finding the hardware implementation structure and method of stream input reading instructions, etc.
Inactive Publication Date: 2009-07-08
XI AN JIAOTONG UNIV
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From the applicant's search of the existing literature, no public stream input read instruction design and its hardware implementation structure and method have been found
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[0018] According to the above technical solution, the present invention is actually a processor extension instruction design and hardware implementation structure and method for reading decoded data streams in audio and video decoding programs. The hardware implementation structure includes two 32-bit buffer registers, an address register Addr for reading the code stream, a Flag register, a Left register and two arbitrary shifters.
[0019] Assuming that the number of bits read each time is not greater than 32, two 32-bit buffer registers Buffer0 and Buffer1 are required. The two registers alternately load data from the data Cache, and the flag Flag determines the current buffer register that stores the previous code stream. Specifically, when Flag is 1, Buffer1 stores the previous code stream. When reading the code stream, first read from Buffer1. If Buffer1 is not enough, then read from Buffer0; when Flag is 0, Buffer0 stores the previous code stream, read When taking the code s...
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The invention discloses a design and implementation method of multimedia extension instructions for stream input reading. The method designs four media extension instructions for stream data input and reading in audio and video decoding, and its hardware implementation structure includes two 32-bit buffers. Register, address register (Addr) for reading code stream, Flag flag register, Left register and two arbitrary bit shifters; the extended instruction includes instruction read initialization (Bini), code stream reading (Bread), data loading ( Bload), the current code stream address return (Bpos) constitutes, and design the hardware implementation circuit of the stream data reading instruction and the pipeline division in the processor, and give its specific instruction encoding method based on the SPARC V8 processor , the experiment proves that the efficiency of the extended instruction is 5-8 times that of the hand-optimized SPARC V8 processor instruction. The performance of the processor for multimedia decoding processing can be effectively improved.
Description
Technical field [0001] The invention belongs to the technical field of processor design and is applied to the design of multimedia processors, and specifically relates to a design and implementation method for reading instructions of decoded data stream input (stream input for short) in audio and video decoding. Background technique [0002] In almost all image and video compression standards, such as JPEG, JPEG2000, MPEG-1, MPEG-2, MPEG-4, H.264, when decoding, the encoded information must be decoded first: such as MPEG-1 and MPEG -2 Audio Protocol Layer 3 (MP3) header information and side information include Huffman table, quantization factor and other information used to decode the encoded data. In the decoding process, these bit streams containing encoded information must be read in real time. . figure 1 In order to realize the program flow chart of the stream input function on the 32-bit RISC (using the byte as the reading unit), first determine whether the byte data buffer...
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IPC IPC(8): G06T1/20H04N7/26G06T9/00
Inventor 梅魁志郑南宁吴奇李国辉张元林黄畅
Owner XI AN JIAOTONG UNIV