Self-timing SRAM access control circuit

Abstract

The invention discloses a self-timed SRAM access control circuit, which makes use of two reference bit lines inserted in a SRAM memory array to assist in timing in the process of precharging and equalization and the read operation procedure. The entire self-timed SRAM access control circuit consists of a first reference bit line, a second reference bit line, a monitoring circuit for address translation, a precharging and equalization control circuit and a read-write control circuit. By use of the first reference bit line and the second bit line, the resistance and the parasitic capacitance on the bit lines in the SRAM memory array and the voltage variation for the bit lines in the process of precharging and equalization and in the process of the read operation are simulated. Through the coordination of the first reference bit line, the second reference bit line, the precharging and equalization control circuit and the read-write control circuit, the SRAM access control circuit is capable of conveniently and correctly producing sub-operation control signals to meet the need of high speed, low power consumption and correct result of the SRAM access operation.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a self-timing SRAM access control circuit for a Static Random Access Memory (SRAM). Background technique [0002] Static random access memory (SRAM) has the advantages of high access speed and low power consumption, and is widely used in the cache between the central processing unit CPU and the main storage system, and the storage system of low-power electronic systems. [0003] The composition of SRAM is as figure 1 As shown, it mainly includes: storage array, precharge and equalization circuit, row and column decoding circuit, read and write circuit, access control circuit, etc. The following briefly introduces each part. [0004] A memory array composed of a plurality of memory cells arranged in a regular structure of rows and columns occupies 50%-70% of the area of ​​the SRAM circuit. Common memory cells include a six-transistor structure, a four-transistor plus two res...

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Problems solved by technology

[0026] 3) Because the data output drive circuit needs to drive a heavy load, which is generally a bonding block of an integrated circuit or a data bus, the output current of the data output drive circuit is very large

Moreover, because the actual resistance and parasitic capacitance on the word line and bit line can only be obtained through the parasitic parameter extraction tool after the semiconductor process to be used is determined and the physical design (layout design) of the memory array is completed, the design longer period

In addition, when the design of the memory array of the SRAM circuit and the semiconductor process adopted change, the access control circuit needs to be redesigned

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