Method for increasing RAM read-writing efficiency

Abstract

The present invention relates to a method for improving the read-write efficiency of RAM in the technical field of communication. The method comprises: firstly, providing a plurality of queues, storing the address of each cell and the information of the number of used banks in sequence; The banks of RAM that can be used in each queue are searched in turn until the first available unit is searched or all the units of the queue are searched and stopped; according to the order of the queues, the first is searched from all available units searched by the clock. The read / write operation is performed on an available bank that does not conflict with the previous read / write operation. The invention effectively avoids the problem of bank conflict in the read and write operations of the DDR-RAM, improves the read and write efficiency of the external memory, and does not increase additional storage space at the same time.

Description

technical field [0001] The invention relates to the technical field of communication, in particular to a method for improving the read-write efficiency of RAM. Background technique [0002] When operating DDR_RAM (double data read-write RAM), limited by its conditions, the operation of the same bank (unit) must wait for a certain amount of time. Taking RLDRAM II (DDR_RAM with simplified latency) as an example, for RLDRAM devices, the relevant operating conditions are shown in the table below. [0003] [0004] It can be seen from the above table that even under the 200M clock, it takes at least 4 cycles to perform the second operation on the same bank. In this way, certain difficulties are brought about when the packet length of certain bytes is read / written outside the chip according to the address. For example, for RLDRAM devices, an address has 8 banks. If each packet length occupies (8×N+1) banks, 3 bank wastes of cycle waiting time will be consumed between packets...

AI Technical Summary

Problems solved by technology

[0010] (1) It is only suitable for write operations, and cannot solve the tRC conflict of the read operation itself;

[0011] When reading DDRRAM, since the address and Start_bank are fixed and cannot be allocated dynamically, it will inevitably affect the efficiency of the read operation

If the pointer recycling scheme is used in cache management, when the Buffer is full, it will also affect the write operation

[0012] (2) Added additional storage space;

[0014] Therefore, none of the existing technologies can fundamentally solve or avoid the waste of bandwidth caused by tRC

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