Test substrate, test substrate mask and test substrate forming method

A mask pattern and substrate technology, which is applied in the field of test substrate, test substrate mask and test substrate formation, can solve the problems such as difficult to ensure the removal effect of passivation layer, oxide residue on the surface of passivation layer, design size deviation, etc. To achieve the effect of inhibiting the phenomenon of oxide residue on the surface of the passivation layer

Active Publication Date: 2009-12-30
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology

[0006] However, in production practice, when the passivation layer is used as a polishing stop layer to planarize the shallow trenches after filling spacers, if the gap between the passivation layers isolated by the shallow trench isolation regions If the size difference is too large, it is easy to cause oxide residue on the surface of the passivation layer with a larger size, so that it is difficult to ensure the removal effect of the passivation layer in the process of removing the passivation layer to obtain the active region, and then causing the actual size of the active region to deviate from the design size

Method used

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  • Test substrate, test substrate mask and test substrate forming method
  • Test substrate, test substrate mask and test substrate forming method
  • Test substrate, test substrate mask and test substrate forming method

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Embodiment Construction

[0056] Although the invention will be described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it should be understood that those skilled in the art can modify the invention described herein and still achieve the advantageous effects of the invention. Therefore, the following description should be understood as a broad instruction for those skilled in the art, rather than as a limitation of the present invention.

[0057] In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as changing from one embodiment to another in accordance with sy...

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Abstract

The invention relates to a test matrix, which includes at least one continuous test unit series; the single continuous test unit series comprises at least two continuous test units; the continuous test unit comprises a basic test element and an auxiliary basic test element; the basic test element and the auxiliary basic test element in the continuous test unit series are connected by alternation; the dimension ratios of the basic test elements and the auxiliary basic test elements comprised by different continuous test units in the same continuous test unit series are the same; the dimensions of the basic test elements and the auxiliary basic test elements of the neighboring continuous test units are gradually changed. A proper technique window can be obtained by testing the remaining of the oxides on the surface of a passivation layer so as to restrain the oxide remaining phenomenon on the surface of the passivation layer from being generated.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a test base, a test base mask and a method for forming the test base. Background technique [0002] In the traditional integrated circuit process, in order to ensure the quality of the product, inspection is required after performing many steps involved in the process, such as the inspection of the product after the grinding or etching process. Usually, a test matrix is ​​fabricated on a semiconductor substrate, and then the test matrix is ​​used to replace the product for testing. In order to enable the test base to truly simulate the related process of the product, the test base and the product are produced synchronously. [0003] Various attempts have been made in the industry regarding the structure of the test base and how to use the test base to perform process inspection and then complete the manufacture of semiconductor devices. The Chinese pate...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544H01L21/00G03F1/14G03F1/44
Inventor 邓永平
Owner SEMICON MFG INT (SHANGHAI) CORP
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