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X87 structural microprocessor

A technology of microprocessor and architecture, applied in the direction of electrical digital data processing, digital data processing parts, data processing according to predetermined rules, etc., can solve the problems that do not include floating-point fusion multiplication and addition instructions, etc.

Active Publication Date: 2010-01-06
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the instruction set of the most mainstream X86 architecture microprocessor currently does not contain floating-point fused multiply-add instructions

Method used

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  • X87 structural microprocessor
  • X87 structural microprocessor
  • X87 structural microprocessor

Examples

Experimental program
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Embodiment Construction

[0019] refer to figure 1 , the structural block diagram shows a microprocessor 100 of X86 architecture whose instruction set includes X87 Fused Multiply-Add (FMA) instruction. The microprocessor 100 includes an instruction register 102, which caches program instructions fetched from a system memory coupled to the microprocessor 100. According to the present invention, the program instructions include X87 fused multiply-add instructions. The microprocessor 100 further includes an instruction fetcher 104 coupled to the instruction register 102 for fetching program instructions from the instruction register 102 and the system memory. The microprocessor 100 also includes an instruction decoder 106, coupled to the instruction fetcher 104, which decodes the obtained program code of the instruction set of the microprocessor 100, such as the X87 fusion multiply-add instruction described in the present invention. . The instruction scheduler 108 is coupled to the instruction decoder 1...

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Abstract

The present invention is about an X87 fusion multiplication and addition instruction in an X86 system structure micro-processor instruction set. The fusion multiplication and addition instruction appoints a first and a second operation numbers to two registers of stack top of the X87 floating-point unit register stack, and appoints a third operation number to a third register of the X87 floating-point unit register stack. The micro-processor multiples the first and the second operation numbers so as to generate product, and adds the third operation number and the product so as to generate result. The result is stored into the third register, and the front operation numbers are ejected out the register stack. In another embodiment of the present invention, the third operation number is appointed to store into the second register below the stack top of the register stack, and the result is also stored into it. The value of the instruction operation code is in the X87 instruction operation code range.

Description

technical field [0001] The present invention relates to a floating-point instruction executed in a pipeline microprocessor, more specifically, a fusion multiply-add instruction executed in an X87 instruction set architecture. Background technique [0002] The instruction sets of some microprocessors, microcontrollers, and digital signal processors include a Fused Multiply-Add (FMA) instruction. A floating-point fused multiply-add instruction multiplies two floating-point operands (A and B) and adds their product to a third floating-point operand (C), namely: [0003] FMA(A, B, C) = (A*B)+C [0004] A microprocessor that includes a fused multiply-add instruction in its instruction set improves the speed and accuracy of many important operations involving multiply-accumulate, compared to a microprocessor that requires the program to execute a single multiply instruction followed by a single add instruction , such as matrix multiplication, dot product operations, or polynomia...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/302
CPCG06F7/483G06F7/5443G06F9/30014G06F9/30163G06F9/30145G06F7/78
Inventor G·格伦·亨利特里·帕克斯蒂莫西·A·埃利奥特
Owner VIA TECH INC
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