Memory and method for refreshing memory array

A memory array and memory technology, applied in static memory, digital memory information, information storage, etc., can solve the problems of high refresh rate and high power consumption

Inactive Publication Date: 2010-02-03
NXP USA INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

A fixed refresh rate may require higher power consumption than is necessary for reliable operation of battery-backed memory

Method used

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  • Memory and method for refreshing memory array
  • Memory and method for refreshing memory array
  • Memory and method for refreshing memory array

Examples

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Embodiment Construction

[0014] In general, the present invention provides a memory with a variable refresh control circuit that includes a plurality of test memory cells in order to determine an optimal refresh speed for the memory that gives reliable performance and lower power consumption. A variable refresh control circuit includes a plurality of test memory cells. In one embodiment, each of the plurality of substantially identical test memory cells includes a capacitance for storing a charge representing a stored logic state, and each of the plurality of test memory cells is connected to the other test memory cells Refresh at different speeds. A monitoring circuit is provided for monitoring a stored logic state of each of the plurality of test memory cells, and in response, a refresh rate of the plurality of memory cells is adjusted.

[0015] In another embodiment of the present invention, the variable refresh control circuit includes a plurality of test memory cells, wherein each of said test m...

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Abstract

A memory (10) includes a variable refresh control circuit (20) for controlling the refresh rate of a memory array (12) using a capacitor for data storage. In one embodiment, each test cell of a plurality of test memory cells (30, 32, 34, and 36) is refreshed at different rates. A monitor circuit (18) is provided for monitoring the stored logic state of each of the plurality of test memory cells, and in response, adjusting the refresh rate of the memory array (12). In another embodiment, a variable refresh control circuit (20') includes a plurality of test memory cells (70, 72, 74, and 76) thatare all refreshed at the same rate but each of the test memory cells (70, 72, 74, and 76) is implemented to have a different charge storage capacity than the other test memory cells. The monitor circuit (18) monitors the stored logic state of each of the plurality of test memory cells (70, 72, 74, and 76), and in response, adjusts a refresh rate of the memory array (12).

Description

technical field [0001] The present invention relates generally to integrated circuit memory, and more particularly to variable refresh control for dynamic random access memory (DRAM). Background technique [0002] Dynamic Random Access Memory (DRAM) is a well-known type of memory that relies on capacitance to store charges representing two logic states. Typically, each DRAM cell includes a capacitor and an access transistor. The charge stored in the capacitor leaks over time, so that the data stored by the DRAM cell needs to be periodically read and rewritten, or "refreshed." Periodic refresh operations require a large amount of power. [0003] The amount of charge leaked from a capacitor varies greatly with changes in voltage, temperature, and processing. Higher temperatures or voltages cause higher leakage than relatively lower temperatures or voltages. Also, changes in processing can cause larger leaks. Therefore, for a DRAM with a fixed refresh rate, memory cells mu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C7/00G11C11/406G11C29/02
CPCG11C11/401G11C2211/4061G11C11/406G11C29/50012G11C29/028G11C29/02G11C29/50016G11C11/4091
Inventor 约翰·M·博尔甘
Owner NXP USA INC
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