Chip package structure and manufacturing method thereof

Abstract

The invention relates to one kind of a chip package structure and its manufacturing methods. The chip package structure at least includes a loader device and a chip configured on the loader. The loader at least includes a radiation pad with a bearing surface, some guiding feet and at least two biramous bracings. In addition, the above chip includes a number of solder balls polycrystalline-interfaced with the radiation pad, the guiding feet and the biramous bracings of the loader.

Description

technical field [0001] The present invention relates to a chip packaging structure and a manufacturing method thereof, and in particular to a quad flat no-lead (QFN) packaging structure and a manufacturing method thereof. Background technique [0002] With the increasing integration of integrated circuits and the demand for high-performance electronic products, packaging technology is driven to develop in the direction of increasing packaging density, reducing package size, and shortening transmission distance to meet the size reduction of integrated circuit components. and the trend of continuous growth of input / output (Input / Output; I / O) numbers. [0003] There are many types of packaging for integrated circuits, and a very common packaging type is to provide a lead frame first, wherein the lead frame has a chip holder and a plurality of leads disposed on the periphery of the chip holder. Next, the chip is attached to the chip holder and the peripheral pins by using the s...

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Problems solved by technology

[0005] However, the existence of these support bars 104 occupies the space of the four corners of the lead frame 100, so that the guide pins 102 cannot be arranged at the four corners of the lead frame 100, which not only wastes the space of the lead frame 100, but also affects the wires. The architectural design of the rack 100 poses limitations

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