Processor architecture

Abstract

This invention disclose a processing system. A processing system comprises a multiport memory module having N ports, N data communication buses, and N hardware acceleration modules that communicate with a respective one of the N ports on a respective one of the N data communication buses. A first one of the N hardware acceleration modules performs a first processing task on data and transmits the data to the multiport memory module on a first one of the N data communication buses. A second one of the N hardware acceleration modules receives the data from the multiport memory module on a second one of the N data communication buses and performs a second processing task on the data. N is an integer greater than one.

Description

technical field [0001] This invention relates to data processing architectures, and more particularly to multi-ported data memory architectures for processing. Background technique [0002] Typically, data processing can be performed by dividing tasks between software and hardware. For example, some tasks are complex but not necessarily computationally intensive, so performing these tasks in software is sufficient. Other tasks are more computationally intensive, so it is more efficient to use hardware to perform them. Parallel processing can be used to speed up the processing of computationally intensive tasks. Parallel processing can be used for video processing, gaming, complex mathematical modeling, video conferencing, and / or other applications. [0003] Various central processing units (CPUs) and hardware acceleration modules are usually connected together through an on-chip bus. Data transfers between CPUs and / or hardware acceleration modules require high bandwidth....

AI Technical Summary

Problems solved by technology

The processing performance of the processing system 10 is limited by the capacity of the communication bus 24

In other words, the processing speed is limited by the speed and / or bandwidth of the communication bus 24

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