Implementation method for in-Turbo code interweaver

[0044] The technical solutions of the present invention will be further described below with reference to the drawings and specific implementations.

[0045] The present invention adopts a combination of software and hardware implementation method, in the case of using less resources, real-time generation of interleaving or de-interleaving addresses, its core idea is to divide the intra-code interleaver with a length of 40-5114 bits into Several mother interleavers of different lengths are used to construct the corresponding sub-interleavers through blank line pre-deletion technology, and on this basis, by deleting redundant half-line spaces, a Turbo code interleaver of a given length is realized. In the Turbo code interleaving and de-interleaving method of the present invention, the implementation device is divided into two parts: software and hardware. The software mainly realizes the calculation of one-time initialization parameters, and the hardware is used to complete repetitive arithmetic operations. Generation of interleaving addresses or de-interleaving addresses.

[0046]This specific implementation takes the information symbol length K=645 as an example to describe the technical solution of the 3GPP Turbo code intra-interleaver.

[0047] Figure 1 is a flowchart of the software part processing in the specific embodiment. As shown in Figure 1, it includes the following steps:

[0048] Step 101: Calculate interleaving matrix parameters. The interleaving matrix parameters include the number of rows R of the interleaving matrix, the smallest prime number p, the number of columns C of the interleaving matrix, and the primitive root v corresponding to the smallest prime number.

[0049] According to the information block length K, calculate the number of rows R of the interleaving matrix, if 40≤K≤159, then R=5, if 160≤K≤200 or 481≤K≤530, R=10, otherwise R=20, In this specific embodiment, since K=645, R=20;

[0050] Find the smallest prime number p, where p satisfies the formula K≤R×(p+1), and p=37 can be obtained according to the formula;

[0051] According to the information block length K, calculate the number of columns C of the interleaving matrix, if 481≤K≤530, then C=p, otherwise when K≤R×(p-1), then C=p-1, when R× (p-1)

[0052] By searching the prime number primitive root table (see Table 1), the primitive root v corresponding to the smallest prime number p is obtained. When p=37, v=2.

[0053] p

[0054] Step 102, construct the prime number sequence q i , Where i is an integer from 0 to R-1, in this embodiment i is an integer from 0 to 19, constructing a sequence of prime numbers q i Is to select R-1 prime numbers in turn from the primitive root table of prime numbers, each prime number q i Meet (p-1) modq i ≠0, where i is an integer from 1 to 19, and q 0 = 1, therefore q i The sequence can be seen in Table 2.

[0055] q 0 ＝1

[0056] Step 103: Calculate the row base address, the initial base address a of the i-th row i =iC, where i is an integer from 0 to 19; inter-row replacement of the row reference address, the initial reference address of the i-th row after the inter-row replacement satisfies b i =a T(i) , Where i is an integer from 0 to 19, the row reference address b in this specific embodiment i See Table 3 listed.

[0057] b 0 ＝684

[0058] Step 104, delete blank lines, and perform the following operations: if RC-K≥2C, find T(i)=R-1orR-2, and delete the corresponding q i And b i , Otherwise when RC-K≥C, search for T(i)=R-1 and delete the corresponding q i And b i , Otherwise keep the original q i sequence

[0059] From the sequence of prime numbers q i Available, after deleting blank lines, the new sequence q′ i See Table 4:

[0060] q′ 0 ＝7

[0061] Base address b i , After deleting the blank line, a new sequence b′ can be obtained i See Table 5:

[0062] b′ 0 ＝324

[0063] Step 105: Calculate the sequence w i , W i =q i mod(p-1), then w in this specific implementation i See Table 6:

[0064] w 0 ＝7

[0065] Step 106: Calculate the base sequence of permutation within the row. The base sequence s(j) can be completed by real-time iterative calculation, s(j)=M(s(j-1)), where j is an integer from 0 to 35, if M( n-1)+v

[0066] s(0)＝1

[0067] Step 107: Configure the hardware. The software will calculate the column number C of the interleaving matrix calculated in the preprocessing process, the number of new rows after the blank row is deleted, the row reference address and the sequence w i Wait for the parameters, configure to the corresponding register of the hardware, and start the interleaver hardware operation.

[0068] The hardware part is mainly used to implement repetitive arithmetic operations, and will calculate the output parameters according to the software module to generate interleaved addresses in real time. The processing flow is shown in Figure 2, and the following operations are specifically implemented: The hardware calculates the in-row replacement mode V of each row in the column in turn by column i (j) and U i (j), in fact U i (j) is the address offset in the row, and the row reference address b′ after deleting the blank row i After the addition, if it is not above the half-line space, then b′ i +U i (j) Output for the current effective interleaving address and transfer to the calculation of the next effective interleaving address. Due to the blank line pre-deletion technology, there is at most one blank position in any two adjacent lines at different positions. Therefore, the hardware implementation can easily avoid the generated address being above the half-line blank position.

[0069] Since the interleaving and de-interleaving can be implemented by the same method, the present invention focuses on the implementation method of the interleaver, but the principle and algorithm are also applicable to the de-interleaver. The invention divides the implementation of the interleaver or deinterleaver into two parts: software and hardware implementation. The software performs simple and necessary preprocessing, the hardware quickly generates the interleaving or deinterleaving addresses in real time, and the hardware implementation completely avoids modulus or multiplication and division. The operation is replaced by addition, table lookup and necessary logic. The main sequence is obtained by iteration or table lookup. There is no need to calculate the replacement prime number sequence in the specification. A new intra-row replacement method is adopted to support simultaneous intra-row replacement. Iterative calculation of the intra-row replacement mode, and the interleaver blank row pre-deletion technology is proposed. Based on the above characteristics, the present invention generates interleaving or de-interleaving addresses in real time under the condition of using less resources, greatly accelerating the data processing speed of the system, and thereby meeting the real-time requirements of high-speed data communication for the system.

[0070] The above are only preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited to this. Anyone familiar with the technology can easily think of changes or substitutions within the technical scope disclosed in the present invention. , Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.