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Multiplexing a parallel bus interface and a flash memory interface

A technology of flash memory and bus interface, which is applied in the system field of multiplexing parallel bus interface and flash memory interface, and can solve the problems of high cost and undesired incremental cost

Inactive Publication Date: 2007-10-17
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

A very rough rule-of-thumb estimate is about $0.02 per pin
Adding 15 to 40 pins to an I / O controller (or another chip in a chipset) is cost prohibitive in many cases
Even at a fraction of this cost, the incremental cost of adding pins to the chipset for NAND flash parts is undesirable

Method used

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  • Multiplexing a parallel bus interface and a flash memory interface
  • Multiplexing a parallel bus interface and a flash memory interface
  • Multiplexing a parallel bus interface and a flash memory interface

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Embodiment Construction

[0032] Embodiments of the present invention allow chipsets to integrate a flash memory interface (with virtually no added pin cost) by multiplexing selected interface signals over an existing parallel bus interface. In some embodiments, the flash memory interface signals are multiplexed over an existing peripheral component interconnect (PCI) interface. In such embodiments, one or more PCI devices and one or more NAND flash devices may be connected to the same bus. The chipset can dynamically select whether the PCI device or the NAND flash device has access to the bus. In an alternative embodiment, the selection can be made statically, such that either PCI devices or NAND flash devices can be used, but one system cannot use both.

[0033] FIG. 1 is a block diagram illustrating selected aspects of a computing system capable of multiplexing flash memory interface signals over a parallel bus interface, according to one embodiment of the invention. System 100 includes integrated...

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Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for multiplexing a parallel bus interface with a flash memory interface. In some embodiments, an integrated circuit includes a parallel bus interface to communicate parallel bus interface signals. The integrated circuit may also include logic to multiplex flash memory device interface signals and parallel bus interface signals on the parallel bus interface.

Description

technical field [0001] In general, embodiments of the present invention relate to the field of integrated circuits, and more specifically, to systems, methods and devices for multiplexing a parallel bus interface and a flash memory interface. Background technique [0002] The availability of larger (eg, in the gigabyte range) NAND ("NAND") flash memory components makes them attractive for hard disk enhancement and / or replacement. The NAND flash memory unit means a flash memory unit that uses NAND logic gates for its memory cells. These large NAND flash parts also have the potential to be used in other ways, such as replacing existing basic input / output system (BIOS) flash devices. [0003] Platform chipsets (and / or host processors) provide one possible point of attachment for NAND flash components in computing systems. However, current NAND flash interfaces are wide parallel interfaces that consume a lot of (expensive) pins. For example, current NAND flash interfaces typi...

Claims

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Application Information

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IPC IPC(8): G06F13/40
CPCG06F13/4226
Inventor D·哈里曼
Owner INTEL CORP
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