A double-fin channel wrap gate field-effect transistor and its manufacture method

Abstract

The provided double-fin channel enclose-grid FET belonged to MOSFET technique in ULSI comprises: a silicon substrate, a grid anode and multicrystal silicon grid enclosing the channel to form the enclose-grid structure, both source and drain connecting with the substrate, two rectangular-section fins as the channels, and a thick SiO2 layer between the right bottom of channel and substrate. This invention reduces cost and power consumption, provides high-speed and high-performance circuit application.

Description

technical field [0001] The invention belongs to the technical field of metal oxide semiconductor field effect transistor (MetalOxide Silicon Field Effect Transistor-MOSFET) in ultra-large-scale integrated circuit (ULSI), and in particular relates to a double-fin type channel surrounding gate MOSFET and a preparation method thereof. Background technique [0002] With the wide application and high-speed development of integrated circuits, MOSFET technology has entered the nanometer field. When the gate length of conventional single-gate MOSFETs is scaled down to sub-50nm, problems such as poor gate control capability, deterioration of short channel effect, large leakage current and insufficient on-state drive current will become more and more serious. In order to improve the gate control capability of MOSFET (also called device), reduce leakage current, increase on-state drive current, increase switching ratio, and suppress short-channel effect, many double-gate or multi-gate ...

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Problems solved by technology

[0003] However, the reported nanowire devices and nanoscale gate-enclosed devices are either limited by the structure itself, or will bring difficulties in process preparation, etc., so that the advantages of nanowire devices and gate-enclosed devices are often not fully reflected.

[0004] For example, the nanowire Ω gate shown in Document 1 (F.L.Yang, D.H.Lee, H.Y.Chen, et al., "5nm-gate nanowire FinFET", in Symp.VLSI Tech.Dig., 2004, pp:196-197) Devices (as shown in Figure 1(a)-(d)) have the following problems: (1) they are prepared on SOI substrates, and the cost is very high; (2) since the preparation of silicon nanowires requires a very thin top silicon film, The channel on the SOI substrate has the same thickness as the silicon film of the source and drain, as shown in Figure 1(c), which increases the parasitic series resistance of the source and drain and limits the on-state drive current; (3) at the same time, the silicon nanowire The cross-sectional structure of the device along the vertical direction of the channel is an Ω gate structure, as shown in Figure 1(b) and (d), it is not a surrounding gate structure, and the gate control capability needs to be further improved

[0006] However, this double nanowire ga

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