Method and circuit for sampling data

Abstract

The invention provides a sampling data method. The method includes: providing a first data and a second data; providing a first clock and a second clock. Using the first clock detects the phase of the first data, using the first clock samples the second data. Using the second clock detects the phase of the second data, and using the second clock samples the first data.

Description

technical field [0001] The present invention relates to a clock and data recovery circuit, in particular to a data recovery circuit which can use an input data frequency divider to divide the frequency of input data to reduce the frequency of the required clock and its related method. Background technique [0002] Generally, the data stream received by the receiver is not synchronous; therefore, for subsequent data processing, timing information, such as a clock, must be extracted from the data to allow its The subsequent synchronous operation; in addition, the timing of the data must be readjusted (data retiming) to remove the jitter accumulated in the transmission. Therefore, the aforementioned clock extraction and data timing adjustment are called "clock and data recovery". However, clock and data recovery circuits must meet strict specifications defined by relevant receiver standards, which poses a major challenge in system and circuit design. [0003] Clock and data r...

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Problems solved by technology

Then, another disadvantage is that in the aforementioned structure, the clock frequency must be maintained at a very high operating frequency, so as to be able to match the input data D in high data frequency; this means that the system must build a controllable oscillator (such as a voltage-controll

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