Method of manufacturing semiconductor device

Abstract

A method of manufacturing semiconductor devices includes forming a trench in a predetermined region of a substrate. A first insulating layer and a second insulating layer are formed on a entire surface so that the trench is gap-filled. The first and second insulating layers are polished until a top surface of the substrate is exposed. A wet etch process of a low selectivity is performed, so that a portion of the first insulating layer remains on sides of the trench while stripping the second insulating layer. A third insulating layer is formed on the entire surface, so that the trench is gap-filled, thereby forming an isolation structure.

Description

technical field [0001] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which isolation trenches can be completely gap-filled without voids. Background technique [0002] Local Oxide Isolation (LOCOS) and Shallow Trench Isolation (STI) are two common methods for creating isolation structures. As the integration level of semiconductor devices increases, the process of forming isolation structures becomes more difficult, especially for the LOCOS method. Therefore, an isolation structure of a highly integrated device is formed by forming a trench in a semiconductor substrate and filling a gap of the trench by a shallow trench isolation (STI) method. [0003] The STI method can be achieved in several ways. Taking a NAND flash memory device as an example, one of the methods is to sequentially etch a channel oxide layer, a polysilicon layer and a hard mask layer to form...

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Problems solved by technology

However, there are fewer advantages when applied to 70nm devices because the deposition, wet etch and deposition that must be performed repeatedly increases production time and cost

Moreover, this approach is even more difficult to apply to 60nm devices

In addition, there are reliability problems due to the use of fluorine (F)

That is, during the gapfill process using fluorine (F), fluorine (F) will combine with the channel oxide and cause an increase in EOT (electrical oxide thickness) and an increase in physical channel oxide thickness

Thus, the programming Vt and programming speed of the flash memory decrease

[0007] The second trench gapfill method is also problematic in terms of device reliability and material cost due to increased unit cost determined by the type of SOD material used

That is, due to the impurities contained in the SOD material, the quality of the channel oxide will deteriorate

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